Benjamin Carr, Ph.D. 👨🏻‍💻🧬Aug 10, 2025
#AMD’s #MagnyCours and #HyperTransport Interconnect: High Core Count Blast from the Past
Magny Cours chip is basically two #PhenomII X6 #CPU dies side by side. Two dies are connected via HyperTransport links, which previously bridged multiple sockets starting from the K8 generation.
Technologies available in the late 2000s made core count scaling a difficult task. Magny Cours employed a long list of techniques to push core counts higher while keeping cost under control.
https://chipsandcheese.com/p/amds-magny-cours-and-hypertransport
AMD’s Magny Cours and HyperTransport Interconnect: A High Core Count Blast from the Past

Today, we’re used to desktop processors with 16 or more cores, and several times that in server CPUs.

Chips and Cheese
Show threadJauntyWunderKindMay 8, 2018
the hope is that in the future, all these dedicated processor interconnects can be outmoded via some gobs of #GenZ or #OpenCAPI or #CCIX (or #HyperTransport 4 #HTX - #InfinityFabric released - make my day AMD!) that allow for more ad-hoc disaggregation & configurations. i don't even really want coherency, just some vaguely #infiniband like #rdma across remote chips, spread out across a board or larger chassis.