Mei Lin 
Finished a bit of a boilerplate design for the MVE-16, an emulator for my #dwmc16 homebrew mini computer.
No functionality at the moment, just a pretty TUI to look at.
@[email protected]
I think I will attempt to reply to the initial post of my WordPress page, whenever I write a new post concerning the design of my #DWMC16 #DIWhy #Minicomputer.
Which for some reason does not manage to ever get a clickable link... >_>
https://dwmc-16.net/2024/05/20/dwmc-16-design-part-6-clock-cycles-and-opcode-design/
MeiLinDWMC-16 Design Part 6: Clock Cycles and OpCode Design
Clock & Instruction Cycles
The execution of all operations are split into phases called instruction cycles. The various types of instructions have a varying number of instruction cycles.
Each instruction cycle takes at least two clock cycles to complete.
Instruction Fetch Cycle
The first Instruction Cycle is the Instruction Fetch […]
https://dwmc-16.net/2024/05/20/dwmc-16-design-part-6-clock-cycles-and-opcode-design/
@[email protected]
Just for anyone who wants to take a look at my latest work on my #DWMC16 #DIWhy #MiniComputer project...
Just for anyone who wants to take a look at my latest work on my #DWMC16 #DIWhy #MiniComputer project...
DWMC-16 Design Part 6: Clock Cycles and OpCode Analysis
Clock & Instruction Cycles
The execution of all operations are split into phases called instruction cycles. The various types of instructions have a varying number of instruction cycles.
Each instruction cycle takes at least two clock cycles to complete.
Instruction Fetch Cycle
The first Instruction Cycle is the Instruction Fetch […]
#d8d4cf #Design #DWMC16 #e8e6e3
https://dwmc-16.net/2024/05/20/dwmc-16-design-part-6-clock-cycles-and-opcode-analysis/
DWMC-16 Design Part 5c: Special Register Simplification
So, I have done some thinking, concerning my decision to add four Index/Offset Registers/Secondary Stack Pointers. And since I want to be able to write a nice, simple version of Forth for the DWMC-16… I decided that I would throw the Special Registers out of memory and put them into the second Register Bank, where I can do a bit more with them, without the need …
https://dwmc-16.net/2024/01/09/dwmc-16-design-part-5c-special-register-simplification/
DWMC-16 Design Part 5b: Secondary Stack Pointers Addition
With the last Post, I decided that I would modify the system a little, with a modification to add nor three bit four Secondary Stack Pointers, simply by removing the PC Offset Register from the Special Registers. This does not however mean that I remove the relative jumps, those are dealt with separately.
Special Use Registers
The Special …
https://dwmc-16.net/2024/01/08/dwmc-16-design-part-5b-secondary-stack-pointers-addition/
DWMC-16 Design Thoughts and Ideas Part 1: Going Forth with Stack Pointers
This post is the result of me listening to this week’s episode of the Advent of a computing podcast, the Jupiter Ace. The Ace was a small micro from 1982/83, designed by two guys that worked on the software and hardware of the Sinclair ZX-81. The hardware was pretty much the same as the ZX-81, but it had one big difference.
Instead of BASIC, the Ace ran …
https://dwmc-16.net/2024/01/04/dwmc-16-design-thoughts-and-ideas-part-1-going-forth-with-stack-pointers/
Mei LinThinking more about #Forth and my #DWMC16, I realised something...
The CPU of the DWMC-16 is almost tailor made for Forth... Because I wanted to have an easy time to write a multi threaded OS, I added three Stack Pointers to the CPU.
SP0 is fixed to be used for jumps and the like for the system itself, but SP1 and SP2 are freely usable with push and pop.
So implementing Forth should be a breeze without any need to resort to programming black magic
Continuing my work on my #DWMC16 project might be currently on hold, due to holidays and a very acute case of Factorio... (The Factory Must Grow!)
But, with the recent episode of the Advent of Computing podcast on the Jupiter Ace, I am wondering whether or not I should integrate a full on Forth compiler into the BIOS...