One challenge was the address bus between multiplexers and DRAM. I'm keep to preserve the layout from the prototype which with the CPU 'plexers at the top (U30, U31) and video 'plexers at the bottom (U40, U41) with RAM in a grid between them.
The obvious route would have been to fork the signals to run down each column of RAMs. But forks create reflections. And these are driven from either end so I'd end up with loops.
I ended up snaking them left then right. Not ideal but better.
Over the weekend I routed the main data bus between CPU, expansion port and RAM inputs etc., the RAM data bus, control signals to the expansion port, and signals within the RAM and multiplexers.
Today I've been adding the long distance signals between I/O and CPU and their origins, as well as those to the 'tape port' connector (to the cassette deck and speaker in a CPC).
Added:
CPU and ROM (top)
Expansion connector (bottom-right)
RAM (left)
Control logic (centre)
And routed the address lines.
There's more room left that I was expecting so I'm being less stingy with chip spacing. I'm hoping I don't regret that!
I found there was room to return to a ZIF socket for the ROM, which will be very helpful!
I'm doing a lot of pin remapping to ease the routing.
Next to see why Kicad isn't drawing the board outline. It turns out the footprint for the audio jack include board edges. It's a low profile socket with the port below board level. But Amstrad mounted the socket slightly forward of the board, cutting some mounting lugs in half.
I've tweaked the footprint to remove the board edges, and added some 'nibbles' for the mounting lugs.
After far too mush hassle the printer port is now routed.
Amstrad schematics claim it's a 36-way connector, even in a 6128. It's not. It's 34! That gives an off-by-one numbering error on the rear pins. And there's few discrepancies between schematics and PCBs, largely over which pins are grounded. I've copied from an actual machine.
I've also tightened up the gaps between traces for joystick and printer. They're slow signals and I'd prefer board space for other things.
On the #CPCZERO project I've been debating whether to finish designing all the video and interrupt circuitry or whether to do a board as-is with connectors to add video on a daughter board later. The latter potentially needs less board revisions but would add a lot of time while I get the remaining design finished. So I'm going with the first option and starting board layout.
The other unknown is how much space I'll need. But I know things are going to be tight.
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With the RAM sorted I’m moving onto the 6845 CRTC. One fly in the ointment here: it’s I/O cycle maxes out at 1MHz. I’m running the 6502 at 2MHz. I think the easiest solution is probably to slow the CPU to 1MHz when accessing the 6845 but that will mean a few changes to the sequencer.
I note this is the solution used by the BBC Micro (which also uses a 2MHz 6502 and 6845).
Old school DRAMs have a lot of timing requirements. I’ve been validating output from the #CPCZERO sequencer prototype against them - and everything checks out 🙂
Comments in my notes are where the timings depend on other components, such as the multiplexers.
Adding basic 6502 emulation to my gate level logic simulator for the CPC ZERO project. I'm only adding emulation of the various cycle types to validate the rest of the system. Here it's raising an error because the RESET pulse is shorter than the 6502 requires.
The CPC ZERO project has been stalled pending some updates to my gate level simulator. I needed it to be able to handle gate delays so I could properly test the sequencer circuit. Today I've been adding necessary code. All the timing data is currently hard coded into the simulator, rather than loaded from a file, but that's enough for now.
I found the circuit was starting with the shift registers out of phase but a tweak to the reset circuit appears to have fixed things.
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