I'm using another '174 to latch various signals which need to be latched at the same time, and reduce the need for discrete flip-flops. This also helps to ensure CRTCE and PHI are perfectly synced - which is required for access to the 6845.

Pre-generating PHI before latching it at the correct moment organically gives me the PRE_PHI I need for the write signal generation.

The 1MHz PHI is held low when not in ~IO_CRTC to ensure it's correctly phased with the 6502 at the times it's required. 3/3

My solution is for the sequencer to generate a PRE_PHI signal slightly in advance of PHI. Combining this with RWB gives a write signal with workable timing.

However, this brings up the issue of the 6845 CRTC which requires an E(nable) pulse of about 1us, ie. 1MHz for it's read/write cycles. I'm running the 6502 at 2MHz but this requires slowing it to 1MHz for such cycles.

I've done a slight rework of the sequencer to generate both 2MHz and 1MHz PHIs and use ~IO_CRTC to select between.

2/n