I can't think of a match for S3 in RISC-V yet. WiFi + dual core + embedded UART (no external uart or JTAG needed) + >40 GPIOs through a pin MUX + USB host/device mode (full speed only. meh) + "paging" for RAM/Flash over OSPI for ~$4USD is just an IoT hobbyists dream.
Espressif fell into the trap of spray-painting yet another C906 (gross) for their upcoming "performance" P4 design, but leaves out their signature radios. Surely they'll fill that gap.
Nice company to work with. ESP32-S3: 🤙
I've spent a lot of time and deffort learning and helping build the RISC-V ecosystem on MCU-class parts. Learning more about the ESP32 ecosystem, it's not perfect, it has a lot going for it. Their naming is terrible, but the ESP32-S3 WROVER-class modules, in particular, are great. Yeah, they know they need to ditch Tensilica and move to RISC-V; they're working on that.
Their doc, code, developer support, libraries, tools are awesome. They will review your board design BEFORE you build it. (1/2)
ESP32-C6 looks hot if you need latest radio standards, but for plain MCU use, S3's dual cores, double the GPIO, huge flash for the same price makes it hard to justify. BL808 or CV1800B are tempting, but are missing Espressif's awesome SDK. ESP32-S3 is just hard to beat for $/CPU.
Show me dual-core RISC-V with ESP32-S3's peripherals at lower price, please. (Meh - I'm buying boards, not chips, and in Qty < 10, so maybe I don't get a vote.)
This young man went SUPER nerdy with his favorite 2D world-building game, #terraria and built a RISC-V RV32I emulator *that passes the conformance tests*. He was then able to build a playable PONG app in #riscv code and run it on this emulator. He learned a LOT about computer architecture along the way. Very impressive.
Normally, spending a summer playing video games would be something I find admirable, but he developed some employable skills in the process.
Porting #Nuttx (with its odd style requirements) to #wch #CH32V demanded producing headers for the parts. Faced with declaring 2303 registers & 4259 bitfields for #CH32v307 alone, I did what any lazy programmer would do and automated it.
The resulting program reads SVD files as produced by #WCH for their #RISC-V parts and spits out ISO C 89 (sigh) headers for the registers.
See https://github.com/robertlipe/svdtoheaders/blob/main/demo/h/ch32v307_reg.h for code a human should never have to write.
RT from Sipeed (@SipeedIO)
Your First High Performance #RISCV #SBC coming~
#LicheePi4A with [email protected] (#TH1520), 8G LPDDR4X+8G eMMC come from $99!
LPi4A will on store in 4.15, preorder now!
https://sipeed.com/licheepi4a
More RISC-V product coming soon! max 16+256, Router, Cluster, Pad, and more, come in Q2!
Original tweet : https://twitter.com/SipeedIO/status/1641820724896624644
My new article on the @Risc-V boards from Sipeed. The M1S Dock ($10 and up) and M0Sense ($4 & up) are powerful, expandable, programmable devices that are shipping now.
https://www.robertlipe.com/sipeed-m1s-dock-and-m0-sense-have-landed/
Also recently, my notes on the BL808 processor used in M1S Dock:
https://www.robertlipe.com/bl808-not-symmetric/
P.S. to @lupyuen : they have sensible bootloaders. Only if you clobber them do you have to mess with BLCube and friends!
Do you have a development board that simply won't boot? Perhaps it was built by "engineers" that don't understand USB-C. Here's the background and three examples of defective design that are (or were) on my workbench.
https://www.robertlipe.com/usb-c-power-issues-with-development-boards/
Some RISC-V architectures have as many as 80 GPIOs. Defining those in KConfigs will be annoying, especially given the current awesome trend of pins being behind a MUX so they can be configured as I...
RISC-V