My wafer.space FABulous FPGA is alive! 👏

This chip was part of wafer.space Run 1 (https://github.com/wafer-space/ws-run1), which taped out at the end of last year.

The video below shows the FPGA starting up and pulsing the two onboard RGB LEDs.
If the video doesn't play, you can also view it on PeerTube: https://makertube.net/w/fBWTsw5hSzG7AaeEb9tMCn

#FPGA #OpenSource #ASIC

It is built using the FABulous (e)FPGA framework and the wafer.space LibreLane template. Everything is 100% open source, down to the silicon. You can find the repository with all the sources here: https://github.com/mole99/gf180mcu-fabulous-fpga

At around 500 LUTs, it's at the lower end of FPGAs. Still, it's capable of a lot, considering that it has 48 I/Os, SRAMs, DSPs, and register files.

GitHub - mole99/gf180mcu-fabulous-fpga

Contribute to mole99/gf180mcu-fabulous-fpga development by creating an account on GitHub.

GitHub
I'm already working on an improved version for wafer.space Run 2 that uses new, community-designed IP blocks.
Submissions for Run 2 are currently open: https://www.crowdsupply.com/wafer-space/gf180mcu-run-2
If you're looking to submit something to the shuttle, no worries if you don't make it in time. You can follow https://wafer.space/ for updates on Run 3.
wafer.space GF180MCU Run 2

Fabricate 1,000 chips of your own design

Crowd Supply

I'm giving a presentation at FSiC (@fsi) in July. Come along if you'd like to see a live demo!

https://wiki.f-si.org/index.php/FSiC2026

FSiC2026

Free Silicon Conference 2026 (FSiC2026) - free and open-source EDA and free and open-source silicon, 6-8 July 2026, University of Ljubljana, Slovenia

F-Si wiki