Ordered an extra VSC8512, the same Ethernet PHY I'm using on my switch project, as microscope food.

I've always been curious what the die looks like especially considering it has a ton of SERDES of several different designs, at least one and possibly two embedded CPUs, a DRAM controller, and is generally a nerfed switch ASIC.

I don't expect to be able to dump the 8051 firmware ROM optically but if I can find at least a rough idea of where it is from the optical images maybe I can come back and SEM it if I get my home delayering setup dialed in a bit more.

@azonenberg a DRAM controller?!
@azonenberg oh I mixed up part numbers, that's fine for a 12-port PHY

@whitequark So as far as I can tell the VSC8512 (12 port 10/100/1000baseT to QSGMII or SGMII) is a fused down VSC742x switch ASIC.

The switch ASIC has a MIPS CPU and a DDR interface.

The PHY version has an 8051 that you can interact with via MDIO to do things like controlling QSGMII SERDES equalizer taps, but so far I haven't found a way to read the code region of memory (I think I can peek/poke all of SRAM though, although I don't currently have a full dump just due to lack of time).

The PHY version has pins labeled DDR_A, DDR_DQ, DDR_VDD, etc that are all supposed to be floated or tied to ground. It's very obviously a nerfed version of the switch SKU.

@whitequark See some more details here https://serd.es/2025/07/04/Switch-project-pt3.html about the rather cursed way to talk to the 8051

I can use the chip just fine as-is but I'm curious what it looks like, and it'd be fun if I could get a rom dump or something out of it (or ideally arbitrary code execution for no reason in particular).

It's 65nm, unsure of foundry but there are some hints it's likely TSMC. The SERDES IP was developed by the "German Design Center" of Vitesse in the Dortmund area.

Switch project, part 3 - what Microchip doesn't (officially) tell you about the VSC8512