I made a bunch of progress reversing the clock-generator section of this XCVU13P #FPGA board last night. I'd like to find a better clock source than the config clock.

The Si5345 clock gen is the center-piece with a Si570 programmable XO as one of the inputs. There's also an SMA input and a diff pair input from the FPGA.

Most of the outputs go to the MGTREFCLK[0] pins for various quads, but OUT8 and OUT9 go to FPGA global clock inputs. That was super promising, but there’s no output on boot 🤨