✧✦Catherine✦✧I would like to formally announce that the #GlasgowInterfaceExplorer revD development (the next iteration: with the same FPGA but 32 digital I/Os and 8 single-ended analog channels that can be configured as 4 differential ones) is well underway with a CrowdSupply campaign planned later this year; stay tuned!
balletproof vest@whitequark will the logic analyzer be back for that?
@nyankat yes; the LA needs bigger on-board memory than the 16 KB the FPGA has, which in turn needs HyperRAM (revC, as an addon) or Octal SPI RAM (revD); once the memory controller is ready, existing revC devices could be upgraded with an addon that mates with the board inside the case, and all revD devices will have it as standard
@whitequark thanks!
@nyankat main thing the memory controller is/was blocked on was the lack of a sound design methodology for designing complex serial I/O interfaces in Amaranth, but I came up with it in the last 1-2 years so that's now ok