impedance is stored in the ball grid array

@gsuberland i'm screaming internally at the cracks in the die and the poor surface finish on the polish.

Like it probably gets the point across, but come on have a bit of pride in your work and do a good job with sample prep

@gsuberland I get upset with myself when I do a package cross section and I can see a hairline scratch in the silicon under 100x magnification rather than a flawless mirror finish
@gsuberland like this QFN is what I consider "eh, it'll do but I'm not thrilled, i've seen better" cross section quality
@gsuberland (the trick to not cracking the die is to go slowly, do the initial cut if any well short of the plane of interest, then use fine grits, like P1200 and smaller, as you approach the target... using a diamond saw or large abrasive to go through the silicon gives exactly the kind of cracks shown in the original image and they tend to propagate pretty far making it difficult to polish them out when you go to finer grits... not that they tried, that surface finish looks like P800 or something)
@azonenberg @gsuberland especially for modern low k stuff, cracks or delam can propagate far
@craigjb @gsuberland I've seen more deep cracks in substrate than BEOL with overly aggressive cross sectioning, but sure that's a consideration as well
@azonenberg @gsuberland Yeah, I’m very much from the packaging perspective, less the FA lab view. Even with 80 or 90 micron streets, a saw will tear up low k without laser groove before dicing for packaging.
@craigjb @gsuberland stealth dicing ftw?
@azonenberg @gsuberland latest thing for us is plasma dicing. For wafer level packaging the die are so small now, even down to 150um on a side.
@craigjb @azonenberg @gsuberland Small!!! That must be what they use for the ICs in the sub miniature phones...