Back, my instance had some server issues and was down for a bit last night.

After some additional etch time, we have this. The die is fully exposed and we can see 88 bond pads, of which 84 are bonded. The package only has 48 pins so there's a lot of multiple bonds (we can see many bonds from the die surface to the ground pad as well).

Even without higher magnification, we can see obvious 8-way symmetry in the die layout, consistent with the "8 ADCs in a trench coat" architecture of the HMCAD1520.

Straight out of the acid, the die was filthy so I sonicated for a few seconds. When that didn't do the trick I left it in for a whole minute, which cleaned it up a lot more but still left some surface debris. The remaining residue is pretty stubborn.

Seen here with Mitutoyo 5x/0.14 objective and combination of low-angle and coaxial illumination

20x/0.42 scan (haven't uploaded to siliconprawn and might not bother since it's still filthy) of the device.

General coloration and appearance is consistent with an older TSMC node (pre 90 nm, when they started to use the distinctive corner fiducial we still see today), and the founder of Arctic Silicon had prior relationships with TSMC, but this is not 100% proof.

It's pretty dirty, but there's three things to point out at this stage:

* The north center of the die is pretty out of focus even in the 20x objective despite me having focused at the corners and done a plane fit. This suggests the sample is slightly warped/flexed to a pretty significant degree.
* There is a large particle of some sort on the southeast corner that hasn't come off during cleaning to date. It's possible this is a scratch or similar but playing with lighting and focus I'm pretty sure it's above the die surface.
* There's an irregular line running north-south along the west edge that might be either package debris or surface damage (inconclusive).

Test patterns in scribe line showing what appears to be source/drain probe points (gate probe point was in the dicing kerf and lost, but you can see the track going to it).

The text is hard to read because there's a bond wire partially obstructing the view and the die is filthy, but it seems to read "0.22 / 0.18" meaning a 220 nm wide transistor with a 180nm channel length.

This is the smallest size I saw in the test patterns, compared to e.g. the 0.22/10 seen to the right, and is suggestive of a 180nm technology node. This is also consistent with the general die appearance.

So at this point I'm ~75% confident it's a 180nm TSMC node although it's hard to be certain since there's no distinctive TSMC fiducial, I don't have an exact match in my library, and the Hittite Microwave qualification report for the part just calls the wafer process "CMOS-C".

The pattern continues, seen here on a different part of the device.

Need to get all this packaging debris off to get a better look at it.

I have to get to work now, first call of the day is in 3 minutes.

But this is good data so far. I've pretty much ruled out at least this sample being an outright fake.

I think this is about as much as I can do with the sample in package since I don't have any NIR / laser / probing capabilities at home.

After work, my plan is to toss it back in the acid with no mask and fully remove the remainder of the package, preserving the leadframe. Ideally I'll end up with a bare die on a copper paddle with 48 little solder lands dangling off bond wires.

If I don't see anything obviously fishy in the bond wires I'll pluck them, then clean the die surface more thoroughly and get some high-res images of the surface and see how it looks.

I'll keep the paddle intact for now both for easier handling (less risk of scratching the silicon if I'm not touching it directly) and to hold the die together in case it's got a hairline fracture I haven't seen yet.

I can easily remove it with hydrochloric or nitric acid in the future if I judge it necessary.