Andrew ZonenbergNov 4

Looking at https://wiki.st.com/stm32mpu/wiki/STM32MP2_boot_chain_overview there's so much secure boot and TEE and uboot and multistage boot chain complexity...

All I want to do is have the bootrom pull a native binary off SPI flash and run it with full privileges, but literally *none* of the docs are written with this use case in mind.

I don't want to run TF-A or uboot or whatever. I don't need secure boot at all.

But this is about par for the course, trying to use a Cortex-A SoC as a very fast microcontroller is probably not the average use case...

Show threaddavidc__Nov 4

@azonenberg
There’s usually no requirement to use TF-A or uboot; though I would recommend you consider uboot as its presence is *really* nice for dev/debug work (TFTP booting an image rather than waiting for a reflash, for example).

I’ve done a fair amount of Cortex-A bootchain work; feel free to ping me if you want.

Show threadDmitriiNov 4

@davidc__ @azonenberg these parts usually let you boot them in USB DFU mode with the right boot pin straps. I assume that can be used without or with a dummy secondary payload:

https://wiki.st.com/stm32mpu/wiki/How_to_load_U-Boot_with_dfu-util#On_STM32MP2_series

You can probably take a look or try to strip tf-a to the basic initial phase (get BL1 to print something) and use that as a starter. Start with a full TF-A and remove bits until you get to a BL1 that writes stuff to a UART, then rewrite as wanted

P.S. feel free to ping me as well, I'm not sure if I can help, but would be happy to try and curious to know

Show threadAndrew ZonenbergNov 4

@dsseng @davidc__ My plan was to do literally the exact inverse. I was going to start with BOOT[3:0] strapped to 4'd3 (development boot) then OpenOCD JTAG a boot image into SYSRAM and execute that.

Then eventually get enough of a stub into RAM that I can burn something to SPI flash and switch to boot mode 4'd11 to boot M33 master from SPI flash and hope it comes up.

Get the M33 talking on a UART and blinking LEDs and then I can work my way up to starting the A35 cluster.

Show threadDmitriiNov 4

@azonenberg @davidc__ do you *really* want to spend your time on developing that stub? I'd just USB-boot U-Boot and use DFU or UMS to flash

Seems the SoC can boot starting from the Cortex-A cores, so following A35-TD boot flow could perhaps be more rewarding as it gets you to the right core directly from the ROM

Show threadAndrew ZonenbergNov 4

@dsseng @davidc__ I'm a lot more familiar with M development so I figured it'd be less work.

I already have a STM32H7 firmware with TCP/IP and SFTP based flashing that I want to use long term.

U-Boot is probably 10x the size of my entire firmware. I don't want the bloat.

Show threadAndrew ZonenbergNov 4
@dsseng @davidc__ For scale, one of my recent STM32H7 + FPGA proejcts had the entire application firmware fit in ~120 kB of flash and compiled from a fresh git checkout in six seconds.
Show threadAndrew ZonenbergNov 4

@dsseng @davidc__ I want to get as close to that level of minimalism as possible while adding the A core and PCIe.

If I could get a GHz M7/M85 with PCIe, I'd do that instead. Nobody makes one, the MP2 looks like the closest thing you can buy today.

Show threadDmitrii

@azonenberg Okay, I studied the tf-a for mp2, and it seems BL2 (the first part the user controls) is responsible for DDR init). So you can build on top of that, or replace that if you need no DDR.

BootROM however should function w/o DDR it seems, so your app can probably deal without it (please verify, pure speculation).

Nov 4 at 7:14pmWeb
Show threadAndrew ZonenbergNov 4

@dsseng The dev board I ordered has DDR but I would really like to avoid the complexity of DDR for my own applications.

Related: I also don't want to use ST's PMIC since I have similar voltage domains on my board for FPGAs and other stuff too. So when I start spinning hardware, one open question is how hard it will be to do my own power distribution and sequencing system (assuming the SoC is running at Fmax all the time so I don't need any dynamic voltage scaling) based on my existing supervisor architecture and probably Murata MYMGK modules.

Show threadDmitriiNov 4
@azonenberg I do not know tbh, but likely the docs have some suggestions on what power sequencing is needed, and whether or not you may leave bits like DDR and GPU unpowered (Not sure if anyone considered running this without DDR ever, but maybe GPU power may be omitted). Another way would be to see how ST PMIC sequences those and make sure your external circuitry matches