Mastodawn

Looking at https://wiki.st.com/stm32mpu/wiki/STM32MP2_boot_chain_overview there's so much secure boot and TEE and uboot and multistage boot chain complexity...

All I want to do is have the bootrom pull a native binary off SPI flash and run it with full privileges, but literally *none* of the docs are written with this use case in mind.

I don't want to run TF-A or uboot or whatever. I don't need secure boot at all.

But this is about par for the course, trying to use a Cortex-A SoC as a very fast microcontroller is probably not the average use case...

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davidc__Nov 4

@azonenberg
There’s usually no requirement to use TF-A or uboot; though I would recommend you consider uboot as its presence is *really* nice for dev/debug work (TFTP booting an image rather than waiting for a reflash, for example).

I’ve done a fair amount of Cortex-A bootchain work; feel free to ping me if you want.

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Andrew Zonenberg

@davidc__ My entire firmware will likely be O(200 kB) so reflashing it should be trivial.

The long term goal is to have a DRAM-less bare metal system with the dual A35s and the M33 each running a while(1) loop running some set of cooperative tasks.

All firmware and data (after initial image load) would live in internal AXI/AHB SRAM; the PCIe would connect to an external Xilinx FPGA.

The dream would be to have one BAR on the FPGA set up for PIO so I just have a hardcoded region of address space on the MP2 bridged to an APB range on the FPGA, with a second range set up for DMA and going to AXI or AXI-Stream on the FPGA.

Ideally, I would be able to use the MP2's hardware DMA engine to send large (kB or more) memory-write TLPs directly to the FPGA and not need to build a DMA engine FPGA side.