What does this mean? It means that we now have a dedicated Matrix ASIC that can be used via standard opcodes/compilers, available to anyone with a relevant toolchain and compiler.

For the most part, expect all of your #BLAS kernels to gain support over time!

For #HPC in contrast with most matrix tile implementations, we have spec mandated single and double precision support.

That's in contrast with the x86 AMX extensions, most consumer dGPU implementations etc. which are 19 bits and below.

If the implementation is anything like previous apple matrix co-processor designs, I expect TFLOPS class dense DGEMM capabilities while drawing sub 20W and only pinning 1 core per sub cluster (those are all very, very good things)

As for SSVE, think of it like a higher throughput, higher latency, subset of the existing ARM SVE and SVE 2 extensions.

As @st01014 correctly asks, we don't yet know how wide the SSVE implementation will be: https://mast.hpc.social/@st01014/112411470296867720

As a *complete* guess, assuming the implementation is similar to prior devices, I'd expect the #M4 #SME and #SSVE implementations to be 512 bits wide.

It's simultaneously possible that Apple doubled the width relative to previous incarnations, and is shipping a 1024b implementation

While using geekbench as any sort of hardcore data source is a fools errand, a doubling of performance for certain operations that would be compute bound in SME are seeing ~2x uplifts on M4.