With the 1000baseT1 boards mostly alive, but no progress on decoding until I get the new coupler board, I'm shifting gears to the trigger crossbar.
Building the back side tonight. Probably won't have time to do the front until tomorrow.
I need to figure out a solution for working with larger boards. This thing is maxing out my current stencil fixture. And my dreams are only getting bigger from here.
Ok, kid is in bed and higher priority stuff dealt with.
The back side shouldn't take too long to populate, it's mostly 0402 0.47 uF bypass caps. There's a few other parts but it goes quick when most are the same value.
Nothing like being two hours into a board assembly and realizing R19 is 15K.
And you don't have any 15K ohm resistors.
Good news is it was a series string and the other was 0 (standard DC-DC schematic for coarse/fine trim) and I had 10K and 4.99K in stock which should be close enough.
Still mad my massive digikey order for this board was missing a jellybean resistor. (I checked the order history and confirmed I never ordered it)
And I'm not doing the front tonight anyway because apparently I don't have the UART level shifter either. Oops.
I usually do a better job of tracking inventory and making sure I have the parts I need when I order a PCB. Not sure what happened this time.
@biggestsonicfan It's probably overkill for the XC7K70T on this board (which also won't be running super hot as I don't have any DDR RAM interfaces, nor am I even using most of the IOs) but I use the same heatsink on the XC7K160T in the same footprint.
It's easier to put an overkill heatsink on simpler boards than to stock separate heatsinks for each prototype that are just barely enough for that project.
@biggestsonicfan Yeah I'm gradually moving towards increasing standardization for a lot of my projects. This is actually the pilot for what I hope to be a common instrument architecture for a bunch of open hardware T&M equipment.
STM32L031 as PMIC and reset controller. STM32H735 as main processor. Big Xilinx FPGA for the primary datapath and high speed stuff, connected to the H735 via quad SPI.
Murata MYMGK series DC-DC modules for power.
Largely common software and gateware infrastructure stack, same external 48V power supply, etc.
@gsuberland The weird looking square LGA? That's a Murata MYMGK series DC-DC converter (you can see one of the black bricks test-placed on the board). I have like five of them to generate all of the required power rails.
They're becoming my go-to for new board designs these day. One or two trim resistors for output voltage adjustment, some bulk MLCCs, and you're good to go. Inductor, mosfet, and small passives all integrated.
@azonenberg I did suspect it was probably a DC-DC given the layout.
certainly not cheap parts but they look very capable.
@gsuberland Also I've spent enough time fighting noise and ripple problems from less nice power supplies or imperfect layout. These give really clean power if you're remotely good about setting them up. One of my rails on a previous prototype had like 4 mV ripple without any additional filtering.
Most of the digital rails weren't quiiite that good but as high power SMPSes go I've been pretty happy with the power quality.
@gsuberland Yep. That was a fairly quiet rail without a lot of other stuff but I was impressed.
Let me grab some screenshots, I still have all of the scopesessions from when I did rail validation...
@gsuberland Here's the 12V0 rail on LATENTPINK (running decently complete firmware passing packets between two of the QSGMII interfaces).
Measured at a bulk cap footprint because the original 12V0 rail test point was right at a SMPS input (before via inductance to the plane etc) and gave unrealistically high noise levels.
@gsuberland 1V2 rail. 1.177 - 1.211V, 34 mV p-p.
Most of this noise is coming from the management port PHY; the ripple drops to 23 mV when the link negotiates to 100M instead of gig.
@gsuberland And here's 1V0, the 1.0V digital core power rail for the FPGA (plus some of the Ethernet PHYs). Cleanest digital rail I've ever seen.
And again, this is not with the board idle doing nothing. You can see an Ethernet frame passing through the switch on the RX0 and TX2 decodes and the rail barely moves.
1.00369 - 1.00657V, 2.87 mV p-p.
@wanderingincode I used to buy 1K by default for jellybean components (unless it was a super expensive high precision resistor, large MLCC, etc) but have started dialing back because I have parts sitting around for so long taking up space on the shelf.
At some point I expect to start seeing yield loss due to oxidation of terminals and will have to rework boards and scrap the affected component inventory. My reel of 33 ohm 0402s from 2014 has already had two or three solder defects that look like poor wetting during reflow (head-in-pillow) and if that number climbs much more I'm gonna have to toss it in ewaste. It's only about half used and I don't expect the parts to still be good in 2034.
So now I've started ordering passives in qty 100 by default unless I anticipate high volume usage (common decoupling/terminating/pullup) in which case I get 1K.
The second bonus of this is that the shorter length of tape lies flat and takes up less space in a storage bin vs a big coil that has to be stored edgewise.
@thomask77 In specialized applications when you are targeting narrowband noise at a specific, known frequency? Yes, you want to match the cap (including mounting parasitics) to have the lowest possible impedance at that frequency which may mean going with a smaller value.
For general purpose broadband use targeting a wide range of frequencies, not so much. ESR/ESL tend to be close to constant for a given package size and construction (e.g. all Murata GRM series 0402s are likely pretty close) with only C varying. So more C will improve decoupling effectiveness if package size is kept constant.
Also keep in mind the difference between voltage *rating* ("the cap won't blow at this voltage") and the *practically usable* max voltage accounting for the C/V curve. Many higher valued MLCCs derate to 20% or less of datasheet capacitance at Vmax.
Higher C in smaller package size means higher electric field strength and a sharper C/V falloff. So a 470n will lose performance faster than a 100 as voltage climbs.
@thomask77 Based on research I did several years ago, and agreeing with Xilinx recommendations at the time, 470n 0402 was a good sweet spot for typical lowish voltage digital logic work in terms of fitting as much C as possible into an 0402 footprint (which fits well across adjacent vias in a 1mm BGA field) without C/V degrading to an unacceptable level.
It's possible that dielectric tech may have improved since and you can get higher values in the same package with decent performance, but I still have several thousand of this particular Samsung part on the shelf so I'll continue to design around it until I run out.
@thomask77 Oh, and also consider package thickness. A lower profile package in the same footprint will have thinner spaced dielectric layers (because less volume to work with) and thus probably worse C/V characteristics.
(Unless they're the same plate stack padded out to a standard thickness and you're just bolting non-functional dielectric to either side, in which case they'd perform ~identically)
Andrew Zonenberg
biggestsonicfan
Graham Sutherland / Polynomial
wanderingincode
thomask77