Reworked all the bridges on the ESD diodes that I found during initial visual inspection, and tidied up a few bulk caps.
Did continuity tests to sanity check on each power rail and nothing is shorted.
Gonna start populating the front side after the little one goes to sleep. Should go faster than the back since it's mostly large ICs not hundreds of 0402s.
I usually begin top side assembly with large but flat components like BGAs so I don't risk knocking tiny stuff around while placing them. Then smaller passives and ICs, and tall capacitors and connectors last.
This FPGA is the single most expensive component I've ever put on a board. Shipping an entire tray for one chip might be slight overkill though...
Out of the oven, BGAs all look good under side view optical microscopy (best I can do without X-ray).
Two 0402s needed touchup with an iron due to poor wetting; they were 33 ohm resistors from a reel I've had since 2014 so they might be starting to oxidize too much for my ROL0 flux to handle.
Tomorrow I'll populate the through hole connectors then start the bringup process.
All soldered up and ready to start bringup!
Later today after my little lab assistant goes to bed, that is. She's still a year or two from being ready to take readings off test points for me... Being able to speak in full sentences is probably a prerequisite.
These are just quick phone pics, I'll do some beauty shots with the A7R and macro lens later.
@gorplop Scaled down prototype (14+1 ports) of a future 24+1 or 24+2 port managed Ethernet switch.
Random names are so much less work than the paralysis of trying to come up with something catchy. The full switch will be LATENTRED and the future 10G-with-40G-uplinks version will be LATENTORANGE.
Andrew Zonenberg
polprog68k