I usually begin top side assembly with large but flat components like BGAs so I don't risk knocking tiny stuff around while placing them. Then smaller passives and ICs, and tall capacitors and connectors last.

This FPGA is the single most expensive component I've ever put on a board. Shipping an entire tray for one chip might be slight overkill though...

Out of the oven, BGAs all look good under side view optical microscopy (best I can do without X-ray).

Two 0402s needed touchup with an iron due to poor wetting; they were 33 ohm resistors from a reel I've had since 2014 so they might be starting to oxidize too much for my ROL0 flux to handle.

Tomorrow I'll populate the through hole connectors then start the bringup process.

All soldered up and ready to start bringup!

Later today after my little lab assistant goes to bed, that is. She's still a year or two from being ready to take readings off test points for me... Being able to speak in full sentences is probably a prerequisite.

These are just quick phone pics, I'll do some beauty shots with the A7R and macro lens later.

Fit testing the thermal solution. Looks mostly good, but not permanently mounting it yet. If i find problems early on it'll be easier to rework without a heatsink in the way.

I provisioned for two fans but we'll start with one and see how it goes.

The QDR-II+ heatsink is somewhat sheltered by the RS232 jack and probably won't see much airflow bit heatsinking it was more of a "just in case" vs the FPGA and main PHY which will definitely need it. So i think I'll be OK.

Kid is asleep so it's back to the lab for me.

After a bit of cable management we've got the first signs of life out of the board.

Applied 12V power to the input and it's drawing 3.6 mA. This is normal and expected, as all power rails are supposed to be off at this point other than the raw input and the 3.3V standby rail driven by an LDO to power the supervisor.

Next step is to put some code on the supervisor and start bringing up more power rails.