Reworked all the bridges on the ESD diodes that I found during initial visual inspection, and tidied up a few bulk caps.
Did continuity tests to sanity check on each power rail and nothing is shorted.
Gonna start populating the front side after the little one goes to sleep. Should go faster than the back since it's mostly large ICs not hundreds of 0402s.
I usually begin top side assembly with large but flat components like BGAs so I don't risk knocking tiny stuff around while placing them. Then smaller passives and ICs, and tall capacitors and connectors last.
This FPGA is the single most expensive component I've ever put on a board. Shipping an entire tray for one chip might be slight overkill though...
Out of the oven, BGAs all look good under side view optical microscopy (best I can do without X-ray).
Two 0402s needed touchup with an iron due to poor wetting; they were 33 ohm resistors from a reel I've had since 2014 so they might be starting to oxidize too much for my ROL0 flux to handle.
Tomorrow I'll populate the through hole connectors then start the bringup process.
All soldered up and ready to start bringup!
Later today after my little lab assistant goes to bed, that is. She's still a year or two from being ready to take readings off test points for me... Being able to speak in full sentences is probably a prerequisite.
These are just quick phone pics, I'll do some beauty shots with the A7R and macro lens later.
Fit testing the thermal solution. Looks mostly good, but not permanently mounting it yet. If i find problems early on it'll be easier to rework without a heatsink in the way.
I provisioned for two fans but we'll start with one and see how it goes.
The QDR-II+ heatsink is somewhat sheltered by the RS232 jack and probably won't see much airflow bit heatsinking it was more of a "just in case" vs the FPGA and main PHY which will definitely need it. So i think I'll be OK.
@wackyvorlon 14x 10/100/1000baseT + 1x 10Gbase-R SFP+ managed Ethernet switch. FPGA based fabric (so fully open source packet datapath) rather than using a switch ASIC.
This is a scaled down prototype for a planned 24 port 1U version.
@wackyvorlon Because I can? Lol. That, and my Cisco 24 port edge switches are getting a bit long in the tooth and I need more baseT ports on my main lab bench.
A homebrew switch has been on my projects list since 2012 or so. My first board was a 4 port switch built around a 25k cell Spartan-6 but a combination of board design issues, lack of FPGA space, lack of experience, and lack of proper test equipment meant it never worked.
Over the years I've built various bits and bobs, got better at FPGA design, and got better test equipment so I can actually test it.
@wackyvorlon https://www.digikey.com/en/products/detail/amd/XC7K160T-2FBG484C/3911021
Currently sells for $435 although I ordered it back in 2021 so price may have been a bit different then.
Putting it in the toaster oven was still a bit nerve wracking no matter how many times i double checked.
@azonenberg Just ran across this FPGA. I had no idea ones this expensive even existed…
https://www.digikey.ca/en/products/detail/amd/XC7K410T-2FFG900I/3543163
@wackyvorlon You think that's big? Look up the XCVU9P lol.
Needless to say I won't be using one in a design any time soon
@wackyvorlon ASIC R&D mostly. If you're spending many $M on a new SoC or GPU design, spending a few bucks on prototyping hardware is not going to break the bank.
Also, Digikey markups for expensive chips in low volume are insane. The devkit for that $50K chip is like $8K so I have to assume they charge big clients even less than that per chip. Expensive, but if you're Qualcomm or Apple or Nvidia you can easily afford racks full of them to support a big project.
@azonenberg @wackyvorlon XCVU57P goes brrrr 😬
„Hey, eh, Boss, that strange new BGA chip, I broke that while soldering, is that an issue?“ 😹
@wackyvorlon Yeah it's the biggest FPGA I've used in a design.
I own larger ones (an XC7A200T on an AC701 dev board, an XC7A200T in inventory that I haven't made a board for, and a pair of XCAU25P's also in inventory), and have used an XCVU9P on somebody else's dev board, but haven't done a board design for any of those yet.
Spec wise the XC7K160T has 101400 LUT6s, 202800 flipflops, 600 DSP slices (25x18 bit multiplier plus some extra stuff for efficient FIR filter implementation), 325 36 Kbit SRAM blocks, sixteen PLLs, and up to eight 12.5 Gbps SERDES lanes and 400 GPIOs. The package I'm using on this board "only" pins out four of the SERDES (max 10 Gbps in this speed grade), and 285 GPIOs.
Not at all enormous by professional FPGA standards, but roughly 20x the logic capacity of, and significantly faster than, an ice40hx8k.
Andrew Zonenberg
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