Andrew ZonenbergJul 15, 2023

Reworked all the bridges on the ESD diodes that I found during initial visual inspection, and tidied up a few bulk caps.

Did continuity tests to sanity check on each power rail and nothing is shorted.

Gonna start populating the front side after the little one goes to sleep. Should go faster than the back since it's mostly large ICs not hundreds of 0402s.

Show threadAndrew ZonenbergJul 15, 2023
Starting front side assembly. Paste print looks a lot nicer.
Show threadAndrew ZonenbergJul 15, 2023

I usually begin top side assembly with large but flat components like BGAs so I don't risk knocking tiny stuff around while placing them. Then smaller passives and ICs, and tall capacitors and connectors last.

This FPGA is the single most expensive component I've ever put on a board. Shipping an entire tray for one chip might be slight overkill though...

Show threadAndrew ZonenbergJul 15, 2023
All the BGAs and most of the big QFNs done. Still tons of tiny components left, but nowhere near as many as the back had!
Show threadckfiniteJul 15, 2023
@azonenberg What does the Super GPIO LED(?) indicate?
Show threadAndrew Zonenberg
@ckfinite GPIOs on the supervisor MCU (little M0 which runs reset and power rail sequencing). Not to be confused with the main MCU, a much beefier M7.
Jul 15, 2023 at 4:48amWeb