A big thanks to the creators of #TerosHDL open-source #VHDL plugin for #vscode <3
Discovered it today, and the built-in parsing, documentation and state-machine flowchart gen + simulation support will make working on our next task at #CERN a breeze!
For those that are curious, we finished coding the 8051 to spit out data on an SPI bus.
Now we "just" need to add a matching side in the Quench-Detection box!
Without some flowcharts to convey the bigger picture that'd be tough (sparsw docs, yay)
Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.
But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~
Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3
Although we need to figure out some design decisions.
The current code base is... organically grown.
I.. Errr... putting three different but slightly related projects *in the same source folders*, just so you don't have to figure out how to share common libraries...
Mixed with script-autogenerates port maps...???
And there's a scary big 23-table excel file containing vital memory maps. We might have to tweak all 23 tables to keep them in sync or it breaks.
Oh and git can't merge or diff it.
In better news, the #VHDL adventures proceed nicely!
It only took a day to write an apparently fully functional SPI master with RX/TX channels!
For a first-time VHDL programmer who spent about three days reading up on syntax etc., this is a nice start <3
Next up is simulated coms to the other processor!
Since the SPI interface can be abstracted well, all it has to care about is setting the Chip-Select and hurling a few bytes around.
Easyyyy
Xasin, Neira & Mesh