Hacker NewsThe MilkV Jupiter 2/SpacemiT K3 (RISC-V vector compute)
Amand TihonTesting my Palo-Alto Tiny Basic for RV32I by playing a game of startrek. Everything seems to be working as expected!
A big difference from the original TBI is that numbers are 32 bits instead of 16. Thankfully, overflow was always treated as an error, so no issue with old programs.
The instructions doc for this version of startrek was quite hard to find, with many dead and wrong links, including archived 404 pages on the Internet Archive.
cnx-software.com [Unofficial]Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core
Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core
Motor driver IC specialist Fortior Technology has recently introduced the FU75xx dual-core motor control MCU family, pairing a 32-bit RISC-V core and the company’s proprietary 2nd-generation Motor Engine (ME2) core. The RISC-V core is used for parameter configuration and routine processing, while the ME core integrates FOC and CORDIC modules that enable fast calculation of FOC (as quick as 5µs) or square-wave control for sensored/sensorless BLDC/PMSM motors. The chips have an impressive list of peripherals (see specs below) and target high-speed computing and real-time control for robotics and motion systems, such as industrial servo drives, robotic joints, smart home appliances, and new energy vehicle systems. FU75xx MCU specifications: Dual-core CPU RISC-V core @ 48 MHz ME2 motor engine core @ 48 MHz with FOC module and CORDIC module Memory - 12kB SRAM, 4kB PRAM for program execution Storage - 64kB Flash with ECC and CRC, self-program and code protection I/Os
Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
Tao of MacThe MilkV Jupiter 2/SpacemiT K3
This is a fascinating box–so much so that after almost three weeks playing with it, I amassed so much material that I nearly decided to split my review into two parts, but in the e(...)
#ai #hardware #homelab #linux #reviews #riscv #sbc #spacemit
Can ArtucGeorgia Tech's Vortex 3.0 pushes its fully synthesizable RISC-V GPU past compute into graphics. The release adds a fixed-function 3D stack (rasterizer, texture units, output mergers), a Mesa Gallium Vulkan driver, and HIP support via chipStar, all Apache-2.0 and running on FPGA. Blaise Tine started Vortex as a PhD student in Hyesoon Kim's group. For an open GPU you can inspect end to end, where does a fixed-function 3D pipeline matter most: research, or real workloads?
#RISCV #OpenSource
#RISCV #OpenSource
RISC-V International👓🤖 One theme from yesterday's sessions: AI is getting smaller, smarter, and moving closer to the edge.
From Physical AI and the unveiling of Picobello, to custom silicon for smart glasses and real-time AI running directly on smart eyewear, attendees got a glimpse of how AI is moving into the devices we use every day.
And RISC-V is helping make it happen.
Stewart X Addison@ben I presume it was sorted ages ago and not just before the failure?
I've not soldered any headers on myself - while I do have some that are separate all the ones I've used with the connectors have been presoldered (so far)
Related: I do have a soldering iron but I keep thinking about ordering a #pinecil from Pine64 ... For no other reason than it's processor is #RISCV and it's geeky!
Habr 25+Доверенная загрузка без доверия: уязвимость в SoC Ky X1
Так уж повелось, что в Positive Labs исследованиями одноплатных платформ чаще всего занимаюсь я. Задачи при этом бывают разными: где-то нужно включить Secure Boot или Encrypted Boot, где-то — наоборот, проверить устойчивость этих механизмов к атакам. Поводом для этой статьи стала обнаруженная уязвимость в чипе Ky X1 – сердце одноплатника Orange Pi RV2, вышедшего в 2025 году. Уязвимость по праву можно назвать учебной – она простая, а процесс её поиска и эксплуатации – прямолинейный, без сложных трюков и неожиданных поворотов. На её примере разберём, как в подобных устройствах реализуются механизмы доверенной загрузки, где именно возникают слабые места и каким образом подобные ошибки могут быть обнаружены и проэксплуатированы.
https://habr.com/ru/companies/pt/articles/1040996/
#secureboot #orange_pi #hardware #security #vulnerability #hacking #reverseengineering #orangepi #riscv
OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations
OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations
OpenCV 5 open-source computer vision library has recently been released with a brand-new DNN (Deep Neural Network) engine that provides better ONNX coverage and enables LLM/VLM support. The fifth version of the popular CV library also adds support for Intel, Arm, Qualcomm, and RISC-V hardware acceleration, improved 3D vision, and various new core features such as new data types, real N-dimensional and scalar support, and performance improvements. OpenCV 5's DNN Engine OpenCV 4.x supports about 22% of ONNX operators, and the new DNN engine in OpenCV 5 brings coverage to over 80%. That means models with dynamic shapes that used to fail on OpenCV 4.x, should now work, as the 5.x engine was rebuilt around a typed operation graph with proper shape inference, constant folding, and operator fusion. The table below shows the main difference between OpenCV 4.x and OpenCV 5 Since it's quite a big change, to make sure