We're in Paris for RISC-V Summit Europe! Visit our poster exhibition at Island 2.1 (Level -2) and learn more about Codethink's work on RISC-V. 👋
Tomorrow, the team will present ‘Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions’ at 12:45 p.m., Gaston Berger (S2). Find out more here: https://www.codethink.co.uk/articles/risc-v-summit-europe-2025-preview/
RISC-V Summit Europe is just around the corner (12-15th May), and Codethink will be attending
In Paris, we'll be presenting our recent work on big-endian support for RISC-V. This internal project involved patching QEMU and other open source software to enable big-endian operation (without existing hardware support!).
Sound interesting? Read our blog post on the project: https://www.codethink.co.uk/articles/risc-v-big-endian-support-runtime-testing/
See you in Paris!
#RISCV #RISCVEverywhere #RISCVSummitEurope #opensource #qemu
As the dust settles following RISC-V Summit Europe, we've had some time to reflect on our time in Munich.
We always enjoy our work with the RISC-V community, from the engaging talks and speakers we listened to and learned from, to the delegates we spoke to at our poster presentation.
Read our round-up of RISC-V Summit Europe here, including a summary of our presentation: https://buff.ly/3zjvDyQ
(Since #DeepComputing does not appear to be on Mastodon.)
"Early @Ubuntu demo of the new RISC-V Mainboard for
FrameworkPuter at the @risc_v Summit in Munich next week #RISCVSummitEurope. This board uses a #StarFiveTech JH7110 with SiFive RISC-V CPU cores."
Submissions to participate in industry and R&D sessions at this year’s RISC-V Summit Europe are now open!
The deadline to submit your proposal is Monday, March 15. Don’t miss the chance to showcase your work at the #RISCVSummitEurope from June 24-28. https://riscv-europe.org/summit/2024/cfp?hss_channel=tw-2694452875
Original tweet: https://twitter.com/risc_v/status/1749886222103679006
We are excited to announce RISC-V Summit Europe 2024, the event connecting the European movers and shakers that are building the future of innovation on #RISCV. See you in Munich, Germany from June 24-28! https://riscv-europe.org/?hss_channel=tw-2694452875 #RISCVeverywhere #RISCVSummitEurope
Original tweet: https://twitter.com/risc_v/status/1725242587383050519
More than 10 billion chip cores based on #RISCV have shipped! @thenewstack’s @agamsh discussed the latest RISC-V announcements and developments coming out of #RISCVSummitEurope. Learn more: https://riscv.org/news/2023/07/risc-v-finds-its-foothold-in-a-rapidly-evolving-processor-ecosystem-2/?hss_channel=tw-2694452875 #RISCVeverywhere #InTheNews
Original tweet: https://twitter.com/risc_v/status/1691194480945213441
Since its emergence close to a decade ago, RISC-V quickly gained the support of major chip makers, including Apple, which has put controllers in its Apple Silicon. About 10 billion chip cores...
.@risc_v CEO @Calista_Redmond interviewed the #RISCVSummitEurope Diamond Sponsors about their latest updates. Watch the interviews with @Andes_Tech, @Antmicro, @Codasip, @ImperasSoftware, @openhwgroup, @semidynamics, and @VentanaMicro here: https://consent.youtube.com/m?continue=https%3A%2F%2Fwww.youtube.com%2Fplaylist%3Flist%3DPL85jopFZCnbOn_0lajQUMlnLUzA5islD8%26cbrd%3D1&gl=BE&m=0&pc=yt&cm=2&hl=nl&src=1
Original tweet: https://twitter.com/risc_v/status/1690032074265161728
RT from SiFive (@SiFive)
Interested in learning more about the reality of #RISCV in automotive? Check out this panel from the #RISCVSummitEurope to hear SiFive’s Andy Frame and other automotive experts discuss the momentum of RISC-V in this space: https://www.youtube.com/watch?v=PfiZnIdPtcE #NoLimits
Original tweet: https://twitter.com/SiFive/status/1689328196225839104
Codethink
Nicola Tuveri
Matt (It's really me) Hartley
RISC-V