👓🤖 One theme from yesterday's sessions: AI is getting smaller, smarter, and moving closer to the edge.

From Physical AI and the unveiling of Picobello, to custom silicon for smart glasses and real-time AI running directly on smart eyewear, attendees got a glimpse of how AI is moving into the devices we use every day.

And RISC-V is helping make it happen.

#RISCV #RISCVSummitEurope #AI #EdgeAI

The keynote room is set, attendees are filing in, and the energy is building as we get ready to kick off RISC-V Summit Europe 2026.

Take a look below for this morning's schedule and follow along throughout the day for highlights, insights, and announcements from Bologna.

#RISCVSummitEurope #RISCV #RISCVEverywhere

We’re in Bologna 🇮🇹

Member Day + Developer Workshops kick off today, and the main conference starts tomorrow at RISC-V Summit Europe.

Still thinking of joining? You can register on-site at the door (credit card only).

Let’s go 🔥

#RISCVSummitEurope #RISCV

We're in Paris for RISC-V Summit Europe! Visit our poster exhibition at Island 2.1 (Level -2) and learn more about Codethink's work on RISC-V. 👋

Tomorrow, the team will present ‘Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions’ at 12:45 p.m., Gaston Berger (S2). Find out more here: https://www.codethink.co.uk/articles/risc-v-summit-europe-2025-preview/

#RISCVSummitEurope #RISCVEverywhere #RISCV

RISC-V Summit Europe is just around the corner (12-15th May), and Codethink will be attending

In Paris, we'll be presenting our recent work on big-endian support for RISC-V. This internal project involved patching QEMU and other open source software to enable big-endian operation (without existing hardware support!).

Sound interesting? Read our blog post on the project: https://www.codethink.co.uk/articles/risc-v-big-endian-support-runtime-testing/

See you in Paris!

#RISCV #RISCVEverywhere #RISCVSummitEurope #opensource #qemu

As the dust settles following RISC-V Summit Europe, we've had some time to reflect on our time in Munich.

We always enjoy our work with the RISC-V community, from the engaging talks and speakers we listened to and learned from, to the delegates we spoke to at our poster presentation.

Read our round-up of RISC-V Summit Europe here, including a summary of our presentation: https://buff.ly/3zjvDyQ

#RISCV #RISCVSummit #RISCVSummitEurope #RISCVeverywhere

(Since #DeepComputing does not appear to be on Mastodon.)

"Early @Ubuntu demo of the new RISC-V Mainboard for
FrameworkPuter at the @risc_v Summit in Munich next week #RISCVSummitEurope. This board uses a #StarFiveTech JH7110 with SiFive RISC-V CPU cores."

Submissions to participate in industry and R&D sessions at this year’s RISC-V Summit Europe are now open!

The deadline to submit your proposal is Monday, March 15. Don’t miss the chance to showcase your work at the #RISCVSummitEurope from June 24-28. https://riscv-europe.org/summit/2024/cfp?hss_channel=tw-2694452875

Original tweet: https://twitter.com/risc_v/status/1749886222103679006

We are excited to announce RISC-V Summit Europe 2024, the event connecting the European movers and shakers that are building the future of innovation on #RISCV. See you in Munich, Germany from June 24-28! https://riscv-europe.org/?hss_channel=tw-2694452875 #RISCVeverywhere #RISCVSummitEurope

Original tweet: https://twitter.com/risc_v/status/1725242587383050519