tucanae47May 20, 2024
Testing my first #amaranthHDL design with #TinyTapeout 02 from @matthewvenn #ASIC, this design is a Gray code counter, it seems to work although i have some rare glitches maybe "noise" in the output pins, (maybe I also missed to read something or my design has some issue). also playing with the tt02 board is very nice, such a nice job.
PljApr 3, 2024
#amaranthhdl when installing AmaranthHDL and the boards support, should a “pip install .” be run to install using the setup.py?
✧✦Catherine✦✧Feb 11, 2024

me & @mwk just shipped a new Intermediate Representation for #AmaranthHDL!

Amaranth's new IR is designed around an industry-leading netlist format taking into account everything we know about RTL, enabling both analyses and interoperability with other tools

it will be the basis for:
- CDC checking
- whole-design soundness checks
- faster and more reliable simulation, esp. of multiclock designs
and more!

https://github.com/amaranth-lang/amaranth/pull/1102

New intermediate representation by whitequark · Pull Request #1102 · amaranth-lang/amaranth

The new Amaranth intermediate representation is netlist-based and global (spanning the entire hierarchy); this enables analyses that were not viable on the old AST-based local (covering only one hi...

GitHub
marble 弹珠Feb 16, 2023

Got inspired yesterday and wrote a double data rate transmitter and receiver in #amaranthHDL

Most interesting was to learn about clock domains to get a negative edge clock for the receiver part.

marble 弹珠Nov 30, 2022

[ Video of an #amaranthHDL blink example being uploaded to a #chubby75 FPGA board via a #RP2040 #raspberryPiPico running #apolloFPGA ]

(edit: spelling)