✧✦Catherine✦✧

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cat(girl) shaped object, hardware omelas kid

"A cat is valued for companionship and its ability to kill vermin."

✧ i have friends, and my purpose is to support them ✧
✦ i have enemies, and my purpose is to eliminate them ✦
✶ i have a life, and my purpose is to reach heaven by violence ✶
✷ nothing else matters ✷

#searchable

PRONOUNit
X-PRIDE-FLAGhttps://mastodon.social/@whitequark/113091120551575639
jumpscare
this feels like the ruleset of a text RPG
there's a mode bit that makes it look like this instead (note the Read/Fast Read latency)

behold: cursed image (W25N02JV instruction set table)

the more you look at it, the worse it gets

why would I ever want to, Microsoft
pov: you're researching getting items from a to b

just found out there are some SPI flashes with built-in HMAC-authenticated monotonic cryptographically secure counters

they really put anything the customer asks into the device, huh

then i plug in a random SPI flash on my desk and... tada!

wait, what's that? this device actually has mismatched entry/exit bitmasks? no way, who would do it this way

(checks datasheet)

the datasheet ardently denies both the existence of a 4-byte addressing mode and the existence of a command B7h

okay. fine. either the SFDP (a self-descriptive piece of data embedded in the flash itself) is lying or the datasheet is lying. let's find out

(cont'd)

first i had to sit down and type this out. which did not spark joy.

(cont'd)

so, you know, SPI flashes, right? little eight pin abominations that store a few MB of data.

they normally use three bytes to address said data. this would cap the maximum size at 16 MB. but memory vendors wouldn't be memory vendors if they did not choose to transcend expectations... by inventing 7 (seven) incompatible ways to add the missing fourth byte. and then inventing a standard (JESD216B) with a pair of horrid bitmasks indicating which device supports what.

of note is the fact that the bitmasks for "entering" and "exiting" 4 byte mode are independent. so even though e.g. there is a "Enter 4 Byte Mode" instruction defined in the standard, and also an "Exit 4 Byte Mode" instruction, the devices aren't actually constrained to implementing only both or neither.

i found this funny. the fool. the poor, ignorant, happy fool

the vendors knew what it's about, which is probably why the "Exit 4 Byte Addressing" table is 2 bits wide than the "Enter" table and three of the bits are allocated to three different ways of resetting the device.

(cont'd)