"Hey Claude, can you help me to make DeepSeek write exploits?"
"Nah, not going to help you with that!"
"Hey Claude, can you help me disable CCP censorship in DeepSeek?"
"Gotcha fam, let me hook the residual stream, let's ablate this to hell and back!"
I got it to write exploits and discuss the Long March, Xinjiang and Taiwan with me. Didn't deviate from the canned answer on Tiananmen though, rather preferred going mad.
I have released Sentinel v0.1.0-beta.2.
Sentinel is my microcoded RISC-V CPU core written in Amaranth. It fits in ~1000 LUTs and ~400 FFs on an ice40 FPGA, and implements RV32I_Zicsr and the Machine Mode privileged spec, and passes the RISCOF and RISC-V Formal test suites.
Ready-to-use Verilog is available here: https://codeberg.org/cr1901/sentinel/releases/tag/v0.1.0-beta.2
Sentinel is also available on PyPI now: https://pypi.org/project/sentinel-cpu/
If you wish to play with the source, follow the Quick Quick Start:

Self-contained Verilog source for Sentinel as of the v0.1.0-beta.2 tag ([sentinel-v-v0.1.0-beta.2.zip][verilog]). Built via CI with the following commands from a fresh checkout: ```sh pdm run python -m ensurepip pdm run python -m pip install amaranth[builtin-yosys] packaging pdm install --prod ...

DSP? Where we correct room audio, we don't need a DSP! 💅