Claire Huang wrote an undergraduate honor's thesis, supervised by @steveblackburn and @caizixian https://www.steveblackburn.org/pubs/theses/huang-2025.pdf

She uses sampling PEBS counters and data linear addressing (DLA) on Intel chips to attempt to understand the structure and attribution of load latencies in MMTk.

After identifying L1 misses in the trace loop as a significant overhead, she adds prefetching and reduces GC time by 10% or so across a range of benchmarks, and more on Zen4.

Well I wasn't going to write this post until Friday, but I spent a bunch of time beating my head against python versioning issues, and while waiting for things to happen I decided to finish this.

So: Allocation profiling with bpftrace!

https://www.mgaudet.ca/technical/2025/5/28/finding-hot-allocation-sites-with-bpftrace

*tap tap* Is this thing on? Yes? Ok, we are SIGPLAN AV and we're looking forward to seeing you all at @pldi in Seoul and remote!

(This is our new centralized channel for communications, updates and announcements)

Are you interested in getting a PhD in Programming Languages, particularly in both practical and theoretical aspects of gradual typing? Consider working with me at the Australian National University.

PhDs in Australia take 3-4 years and come with a tax-free stipend. See https://users.cecs.anu.edu.au/~fabian.muehlboeck/phd.html for more details.

I am at POPL this week, so if you are there, feel free to find me or coordinate to meet with me via e-mail.