Kristin Davidson {kxd}

29 Followers
56 Following
459 Posts
Bit Transducer. Codes stuff. Plays Games.
💜 Go, Rust, Kubernetes
🏢 @Bitbucket @Atlassian
😇😈 she/her 🏳️‍⚧️ 🏳️‍🌈
📖 me.kxd.dev
Sitehttps://me.kxd.dev
Pronounsshe/her
Bluesky/AT Proto@kxd.dev
Twitter (rarely)@aphistic
@0xabad1dea Ahh, the gender fluid I’ve been hearing about!
@anathema I really wish I could find one of those sedation places around me. I have a bunch to do and also just want it gone.
@misty Are you thinking of going to Linux on your Mac hardware or buying something new?
@misty Whoa, I actually forgot hurd was a thing…
@mntmn I have a remarkable 2 that I’m not using because I got the pro. Or are you specifically looking for the paper pro?
@jacqueline That’s some impressive soldering at least!
@bmac Yeah, my rule is if I feel like you’re emailing me too much you get blocked. Typically that’s more often than once every week. Emailing me more often isn’t going to result in more sales, it’s going to result in less because I’ll block you and forget you exist.
@mntmn Ah, ok. I think that answers another part of my question. You can't go from a newer-gen controller to an older-gen device using fewer lanes on the newer-gen controller...? Since each lane is a physical pair of wires? Like, 4.0 x2 -> 3.0 x4 is not possible directly? Are there ICs you're aware of (or some name) that would allow you to do that type of conversion?
@mntmn Ahh, gotcha! The rk3588 was actually one of the chips I was looking at. The general idea is a device that can transfer CFexpress (or SD UHS-II+) as fast as possible to an m.2 NVMe drive. This is really fast for modern embedded chips, so I was also looking at something like an N150. I'm mainly trying to figure out if I can connect a 3.0 x4 to a 4.0 x2 since it's the same bandwidth but different generations.
@mntmn Hey! I assume you're familiar with PCIE at the hardware level with all your MNT work? I'm trying to understand PCIE design with an ARM chip for a project I have in mind, but I can't find a definitive guide for splitting PCIE lanes and how different generations can be split for best performance. Would you have any suggestions for where I could look?