Exam in #AAPL on Tuesday 2. 9:00 in U2

Deadline for written journals/notes/doc today at noon

Exam format:
We all gather in U2 at 9.00
You the projects in public as groups/individuals (10 min/person).
Everyone are allowed to ask questions. Guests are welcome.
If you prefer private exam, we do that after the public part.
I guess it will take about 4 hours ... be prepared for delays though.

The grades are Passed/Not passed and will be posted after we are all done.

Checked the Qlink sources
Found the likely problem:

The Qlink verison posted turned out to be a temporary test - jerry rigged to use 1mbps by reducing clock freq by factor 3 in mmcm48.vhd

I updated the homepage - Qlink-2026-03-24 is now adapted to Sindri and is tested!

The old stuff probably works with 1mbps - but the clock freq is only 12MHz not 48 .. so get rid of that!!

I included some good assignments in the new source .. they work toward the project!

#AAPL
Tested HDMI with the 2 wires added.
It works like a charm.

As the HDMI outputs are in IO zone 34 and the clock input is in 14, it was necessary to use a BUFG. Also, you need 2 MMCM or PLL to use 12MHz clock to achieve full HD@50Hz as shown on video

I forgot to connect pin 1 and 3 (the blue channel) in the Sindri board.

It can easily be fixed by connecting to the 2 pads:
UTILITY -> PIN1
HPD -> PIN3

As UTILITY/HPD is routed to a pair of differential pins.

Although it requires high-level soldering skills to pull off. So get Brian/Martin to help and limit the number of boards you ask them to help with.

You can now download Qlink from:
https://stengaard.net/Projects/Sindri/VHDL/QLink_2020.zip

It is an entire vivado project
You need to adapt the constraint file and clock frequency to Sindri, for it to work!

Happy hacking - see you tomorrow