Anders Sørensen

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131 Posts
Associate professor, computer systems engineering & Robotics. Teaching cyber-physical systems & assisted living technology at University of Southern Denmark

Checked the Qlink sources
Found the likely problem:

The Qlink verison posted turned out to be a temporary test - jerry rigged to use 1mbps by reducing clock freq by factor 3 in mmcm48.vhd

I updated the homepage - Qlink-2026-03-24 is now adapted to Sindri and is tested!

The old stuff probably works with 1mbps - but the clock freq is only 12MHz not 48 .. so get rid of that!!

I included some good assignments in the new source .. they work toward the project!

#AAPL
Tested HDMI with the 2 wires added.
It works like a charm.

As the HDMI outputs are in IO zone 34 and the clock input is in 14, it was necessary to use a BUFG. Also, you need 2 MMCM or PLL to use 12MHz clock to achieve full HD@50Hz as shown on video

I forgot to connect pin 1 and 3 (the blue channel) in the Sindri board.

It can easily be fixed by connecting to the 2 pads:
UTILITY -> PIN1
HPD -> PIN3

As UTILITY/HPD is routed to a pair of differential pins.

Although it requires high-level soldering skills to pull off. So get Brian/Martin to help and limit the number of boards you ask them to help with.

Almost tgere
#AAPL
Sorry - delayed 15 min.
See you 8.30

You can now download Qlink from:
https://stengaard.net/Projects/Sindri/VHDL/QLink_2020.zip

It is an entire vivado project
You need to adapt the constraint file and clock frequency to Sindri, for it to work!

Happy hacking - see you tomorrow

#AAPL
lets follow up on:
- QLink - I will bring source
- Simulation & testbenches
- Clock systems
- Video HDMI ... what have you found out so far?
#AAPL i U162 på mandag
Denne her er et godt sted at starte med hdmi
https://www.fpga4fun.com/HDMI.html
fpga4fun.com - HDMI

Implementing a TMDS Video Interface in the Spartan-6 FPGA Application Note (XAPP495) - This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan-6 FPGAs - XAPP495

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan-6 FPGAs