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Andres
@andydemski
- 2 Followers
- 59 Following
- 6 Posts
Just another guy
@whitequark i'm not sure. I think it depends on memory layout but i will check.
@whitequark the only differences i found between nands are how to change to slc mode(one has a setfeature flag, and other has a prefix command for every data/address command) and also that nands with pages of 16KB have different addressing (one byte more).
@tnt I don’t know about rpi5 pcie, but I had problem like that when root complex has ssc enabled and the fpga has a fixed ref clock. I don't remember the error I had but I think it stops negotiation at gen1
@andydemski yosys, abc, and nextpnr; we are already able to replace much of yosys but not the rest of the tools yet (and not the Verilog frontend)
@whitequark as all you are involved, this looks amazing! I dont understand if it would replace yosys or if it a different thing.