tntMar 10

Any PCIe expert out there ?

I'd like to skip phase 2&3 equalization when switching to Gen3. Root is a RPi5 and device is a xilinx fpga I control ...

Show threadAndres
@tnt I don’t know about rpi5 pcie, but I had problem like that when root complex has ssc enabled and the fpga has a fixed ref clock. I don't remember the error I had but I think it stops negotiation at gen1
Mar 10 at 9:49pmMastodon for Android
Show threadtntMar 10

@andydemski Yes, if you have SSC you need the use the ref clock from the host.

But not a problem here, RPi5 doesn't use SSC.