Gabriele SveltoMay 24
Regarding the Raptor Lake bug I received a couple of messages from confused users that had read articles on Tomshardware and Neowin. They asked about erratas and microcode updates which puzzled me, because that was part of my early investigation into the bug and we know that the failure is not caused by a known errata and microcode updates cannot fix broken CPUs. So why did they ask? As it turns out it was slop. Both articles are 100% slop full of confusing and inaccurate claims.
Show thread🇺🇦 haxadecimal 🚫👑6d ago
@stman @gabrielesvelto
Vertical microcode really is a lot like assembler, but the majority of microcoded systems (including microcoded microprocessors) use horizontal microcode, which usually takes fewer words of microcode, but much wider. Overall it's usually more total bits, but faster. Horizontal microcode almost always accomplishes more work in a single cycle.
Show threadRaffzahn6d ago

@brouhaha

I'd say it's the same in either case. Horizontal is just more capable by complying with more implied restrictions. In consequence one needs to think even more about each line.

@stman @gabrielesvelto

Show thread🇺🇦 haxadecimal 🚫👑6d ago
@Raffzahn @stman @gabrielesvelto
The few vertically microcoded systems I'm familiar with take _many_ cycles to interpret one macroinstruction, and the cycle time is slow because the narrow, highly encoded micro word needs more levels of logic to decode into the hardware control signals.
Most horizontally microcoded machines take very few cycles per macroinstruction, unless the macroinstruction is quite complex.
Show threadRaffzahn6d ago

@stman @brouhaha @gabrielesvelto

Well, isn't it the same way as an Assembler is specific to a CPU? And boy there are CPU's out there at least as weird as some micro code engine...

Show threadRaffzahn5d ago

@stman @brouhaha

Not really, Of course there are may micro code architectures that use a full figured PC - as well as such with next-pointers or such coding (one or more) next addresses within their word.

Show thread🇺🇦 haxadecimal 🚫👑
@stman @Raffzahn
That's what microcode does, to implement the FSM, except that an instruction doesn't have to only do one thing. Macroinstructions often do more than one thing, so it's not at all a stretch for microinstructions to do so as well.
As with pipelined processors in general, usually the microcoded control unit executes microinstruction n while fetching n+1 (or another branch address).
A good introduction can be found in _Bit-Slice Microprocessor Design_ by John Mick and Jim Brick.
May 26 at 10:55pmWeb
Show thread🇺🇦 haxadecimal 🚫👑5d ago
@stman @Raffzahn
Common examples of processors in which instructions do multiple things include VLIW processors, like the Intel & HP Itanium, and some DSP processors, like the Motorola DSP56000 series. There have been many others; they simply aren't as common as e.g. x86 and ARM.