Mastodawn

This blog post is an extended metaphor that serves as an excuse to complain about Verilog. https://www.cs.cornell.edu/~asampson/blog/buildingblocks.html

Back to the Building Blocks’ Building Blocks

Verilog is the foundation of all hardware design, and it is fatally flawed. We should all be worried about a glut of hardware bugs caused by Verilog’s unpredictable semantics and simplistic type system.