Adrian Sampson5d ago
This blog post is an extended metaphor that serves as an excuse to complain about Verilog. https://www.cs.cornell.edu/~asampson/blog/buildingblocks.html
Back to the Building Blocks’ Building Blocks

Verilog is the foundation of all hardware design, and it is fatally flawed. We should all be worried about a glut of hardware bugs caused by Verilog’s unpredictable semantics and simplistic type system.

Show threadTheZoq25d ago

@adrian

"This footgun has a name: X-optimism. That’s the standard behavior for Verilog: if treats X as false, which incorrectly makes conditional assignments appear defined when they are actually unknown."

TIL, I more and more suspect that my rule about C++ that "Every feature, no matter how trivial, must have a pitfall" applies to Verilog too

Show threadTheZoq2
@adrian Oh my god wat, the justification is _simulator performance_??????
May 26 at 4:33pmWeb
Show threadAdrian Sampson5d ago
@thezoq2 yeah, I was surprised to find that quote! in their defense, the correct semantics do indeed seem slow to simulate… 🤪
Show threadKevin Laeufer5d ago
@thezoq2 @adrian VCS has an option to do the slow but more correct thing. X prop might still be unsound though.
Show threadAdrian Sampson5d ago
@ekiwi @thezoq2 Ah yeah, maybe I should mention somewhere that (despite X-optimism being the official semantics), different simulators disagree and some have configuration options…
Show threadTheZoq25d ago
@adrian @ekiwi Ah, even better!