tntThe #Raspberry #pi5 is sending a 54 MHz PCIe refclock during boot before switching to 100 MHz, this is a bit surprising ...
Marcus Müller@tnt wait, isn't PCIe the family with clocks that are multiples of 25 MHz and maybe 125/2 MHz ?
@tnt so what you're saying is that the polite "a bit" in "is a bit surprising" does a fucking lot of lifting there?
@funkylab Well, it does go to 100 MHz eventually and I thinkg the reset line is asserted until it's a valid 100 MHz signal.
But I'm debugging an issue because on one LitePCIe card the `reset` line wasn't reverse engineered yet and so it's not wired. And so the PLL tries to lock to that 54 MHz signal, goes way out ... and doesn't have time to properly come back when the 100 MHz finally appears. ( That's my theory anyway ).
@tnt well, initializing at some nonstandard, unspecified rate is definitely a big surprise, and yeah, I'd see how intentionally drawing the PLL away as far as possible from the actual future 100 MHz makes it kind of hard to lock.