Mastodawn

I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

Has anyone done a UART in a CPLD?

#LT6502b

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Niels Moseley Apr 12

@PaulaMaddox can you add wait states?

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Paula Maddox Apr 12

@trcwm Already did, stretched to 15 high and 1 low, still broken :(

@PaulaMaddox ugh. 😩

@trcwm the problem is that the AVR takes 5 clock cycles to go into an IRQ and 5 to come out.
With a 1uS stretch I have 20 cycles, but, I also need to “stop” outputting onto the databus at exactly the right time otherwise I get gibberish back or the CPU goes nuts because the instruction is messed up.

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Niels Moseley Apr 13

@PaulaMaddox sounds like a ob for some additional 74xx. I want to halt a Z80 after it writes to an IO port so an external uC can process it. A simple SR flip flop should be able to assert /WAIT when detecting a write. The uC will clear the FF. Perhaps something similar is possible for the 6502?

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Paula Maddox Apr 13

@trcwm yeah, there’s a few ways around it. I’m just thinking about which way to go.
If I can get a uart in the CPLD that would be the cheapest as no extra parts and no board respins (I luckily used the uart pins on the AVR as chip selects so it’s already wired up).