William D. Jones1d ago
πŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘

Does the world need a new single-board computer design with an MC68060 CPU?
I'm thinking about 4GB of DDR3 DRAM, one serial port, one M.2 slot for an NVMe SSD, and one Ethernet port (probably 1Gbps). Not intended to be software-compatible with any existing board or system.

Same question, but various 32-bit RISC processors? MC88110? Am29000/Am29050 (pin compatible)? Intel 80960KA/KB/MC/XA? TI TMS34020?
#retrocomputing

Mar 27 at 7:34amWeb
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago

Probably split into two boards. All I/O and the DDR3 memory controller are provided by an FPGA. The CPU-specific bus interface logic is in the FPGA, using GPIO pins to connect to the CPU pins, so the FPGA/memory/IO board could be used with multiple different CPU boards.

The trick here is that some of the 32-bit CPU chips have more than 150 digital pins to connect to the FPGA board, and off-the-shelf FPGA eval boards rarely offer more than 50 GPIOs. This, a custom FPGA etc. board.

Show threadDaniel Carosone1d ago
@brouhaha ns32k and sh4 just because you didn't mention them, though I might argue that the dreamcast is almost an SBC
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@uep
If I could actually get an NS32532 chip...
I've only programmed SH1, not the later versions.
Show threadI love this, so I1d ago
@brouhaha I’m still seriously thinking about building a FPGA β€˜040 Classic Mac board that takes β€œmodern” DDR3 RAM, USB keyboard, NVMe SSD, etc. and hopefully can be clocked well above what a 68k could ever achieve.
Show threadI love this, so I1d ago
@brouhaha but maybe I need a different approach for a V1 board - BYO real β€˜040 and use a much smaller FPGA that pretends to be the memory (backed by DDR3 RAM) and emulates all the IO
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@jpm
That's what I'm doing. The actual CPUs, just new mem and I/O. Still takes a not-emtotely-trivally-sized FPGA for interfacing to large-ish DDR3 (I really want 4 GiB) and PCIe. An Artix-7 comes close, but my limit the DDR3 size to 1 or 2 GiB.
Show threadI love this, so I1d ago
@brouhaha the bigger pin-count A7 parts can definitely support a single standard DIMM. 434-pin can just but not leave much else. 676 definitely more comfortable.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@jpm
I only want 32-bit wide (or 40-bit incl. ECC), so I was thinking four or five soldered-down x8 parts, though that is much more expensive than a DIMM or SO-DIMM. Maybe a 64-bit DIMM or SO-DIMM is OK, and just terminate the excess data lines?
For 4Gibytes, it looks like rank of 2 is required, because 8Gibit DDR3 parts (1Gi *8) are dual-die.
I'm nervous because I don't have signal integrity tools to check my layout.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@jpm
I think an XC7A100 or 200 in a 484 BGA with 32-bit DDR3 would leave me over 200 GPIO, which is in the range I want. There's a big price jump for the 676 package from Chinese suppliers (e.g. LCSC).
I'm considering doing a test board first with 2MiB of async SRAM (four 512Ki*8) instead of the DDR3.
Show threadI love this, so I1d ago
@brouhaha yeah if you go for 32 bits of hard-wired DDR3 you can get away with a 484, but BYO DDR3 stick definitely has an appeal. The DDR3 clock domain is like an order of magnitude faster than a 32-bit β€˜040, so you can probably get away with physical reads and writes being 64-bit from translated 32-bit logical reads and writes.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@jpm
That would be awesome!
Some of the older RISC CPUs I'm interested in could actually be more efficiently implemented in the FPGA, but I didn't want to attempt to design superscalar cores like the 68060 or 88110. AFAICT, in an FPGA a scalar core but at higher frequency is likely to be better.
Show threadRegionales Retro-Rechenzentrum5h ago
@jpm @brouhaha Thereβ€˜s a new kid in town: FPGA based Transputer Inmos T800 (ATW800/2)
Show threadbig awoo notation4h ago
@brouhaha (this is kinda the plan for Nightcore at the moment; a MIPS R4000 but with a modern ISA)
Show threadPoul-Henning Kamp1d ago

@jpm @brouhaha

If somebody wants to implement an interesting CPU in a FPGA, I have a complete netlist for the Rational R1000 "Ada" computer...

https://datamuseum.dk/wiki/Rational/R1000s400

Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@phloggen @jpm
That does seem like an interesting project. Do you have a complete Rational software distribution to run on the machine?
I had a friend who worked at Rational back then, and I always wanted to play with the machine, but never had the opportunity.
Show threadPoul-Henning Kamp1d ago

@brouhaha @jpm

Yes, we have a set of diskimages of a running system, and also a software emulation which works:

https://codeberg.org/Datamuseum-dk/R1000.Emulator

But it would be so neat to be able to build a 1:10 fpga+rpi driven scale model for desk-top use :-)

R1000.Emulator

Software emulation of the Rational R1000/s400 computer

Codeberg.org
Show thread[tj] - knows what your packets are thinking1d ago
@brouhaha I don't care about anyone else, but I want these.
Show threadbitsavers.org1d ago

@brouhaha

wouldn't a coprocessor to to all the I/O make more sense, especially if it could do hardware debug of your cpu/memory ?

Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@bitsavers
That would go in the FPGA. I don't know of any practical way to interface old chips to DDR3 and PCIe without an FPGA. Pretty much any existing soft CPU core you'd like could be used for a "service processor". I'd probably use a RISC-V, because the tools for that are in reasonably good shape now,. Xilinx even provides a MicroBlaze V core and tools in their software.
Show threadNeko May22h ago
@brouhaha @bitsavers LPDDR3 perhaps?
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘20h ago
@NekoEd @bitsavers
Whatever kind of DDR3 is supported by the FPGA MIG.
Show threadChuck1d ago
@bitsavers @brouhaha
FWIW a "co-processor to all the I/O" is generally referred to as a "channel controller" per the IBM 360 architecture πŸ˜ƒ One of the more fun things about the Intel "systems" architecture that ran over Multibus was that every multibus card had its own processor to do the function of the card, the bus was basically two 32 bit parallel ports and some control lines.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis
A channel is just a fancy DMA controller.
What @bitsavers and I are talking about (I think) is much different than a channel. It's using a processor to act as everything from the electrical bus interface of the target CPU chip up, which could potentially include channels, but most of it wouldn't "be" a channel.
This has been done using e.gm Arduinos for many 8- and 16-bit processors, but I haven't heard of any for 32-bit, possibly due to the large number of GPIO required.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
Doing this with a processor is great to experiment with the target CPU bus interface and such, but would generally run slower than typical target CPU speed.
What I proposed was to use an FPGA, but have a "service processor" in that, which could potentially implement some of the bus protocol for debug purposes, but otherwise would mainly be for system management and debug.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
Mostly I want "actual hardware" in the FPGA, so that once the hardware is intitialized, it can run with little or no support from the service processor. However, the flexibility of the FPGA definitely offers a lot of potential for debugging.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
I've been working on target designs like this for several different obscure processors (not the "common" ones I listed) for ages, and because I'm an idiot, it only recently occurred to me that I could do it as a single, more general platform usable for multiple of the processors that interest me.
Show threadChuck1d ago

@brouhaha

Where do you put the RQDX3? (DEC MSCP controller for the QBus)

@bitsavers

Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago

@ChuckMcManis @bitsavers
The RQDX is a DMA master device, sort of like the Adaptec 1542 for PCs.

Not a channel, because systems that use channels have the channels as distinct functional block (though possibly not distinct physically), and use compatible channels for all devices (or at least all that do DMA), while an MSCP port is its own thing, unrelated to the DMA done by other kinds of PDP-11 and VAX peripherals (e.g., RH11/RH780/etc Massbus, RL11, RK11, etc.).

Show threadChuck1d ago

@brouhaha

That's helpful, I've got a more generalized definition of channel but yours works too.

@bitsavers

Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
I admit that I'm picky about it. The System/360, /370 channels are my baseline for calling something a channel. Aside from a little-used "direct connection" optional facility on some CPUs, _ALL_ 360/370 I/O went through channels. That's one of the things that made virtualization on 360/67 and 370 systems a whole lot easier to implement and more robust than on x86, where I/O interfacing was a total wild-west free-for-all.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
AFAIK, not a single mass-produced device existed that used the 360/370 direct interface option. It was intended for customer interfacing to things without actually having to design a controller to sit on a channel.
Show threadChuck1d ago

@brouhaha That is probably true, although when I interned with IBM on Diagonal Highway in Boulder, CO, they had a film printer connected to the direct interface I/O that was part of a small 370 dedicated to doing layout and fabrication of printed circuit boards.

@bitsavers

Show threadChuck1d ago

@brouhaha
The 360/370 architecture was my introduction to them, and they heavily influenced the rest of the industry. When I took computer architecture at USC they had generalized a channel to be a transport that was generally many to many, that had a protocol that all participants on the channel used to achieve their actions. SCSI met that definition and multi-master SCSI was used in a lot of early high reliability machines.

@bitsavers

Show threadMarsh Ray23h ago
@ChuckMcManis @brouhaha @bitsavers I worked for a company that made channel (bus and tag) and ESCON cards for the PC.
Entirely FPGA-based.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
That said, the RQDX, and MSCP ports in general, are much better architected than all PC bus-mastering devices that predated PCI, and even many that are PCI or PCIe. The only thing even close in the PC universe is NVMe.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@ChuckMcManis @bitsavers
The NCR/Symbios/LSI Logic parallel SCSI host adapters were good, but didn't have smarts to provide a true physical-interface-agnostic storage abstraction, so not in the same class as MSCP.
Show threadbitsavers.org8h ago

@brouhaha @ChuckMcManis

I'm not going to dwell on this, but the major flaw of the channel model is asynchronous comms.

IBM terminal systems work the way they do for a reason.

Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘4h ago
@bitsavers @ChuckMcManis
At some point, IBM channels developed a way for a controller on a subchannel to disconnect from a computer-initiated I/O request, freeing the channel to be used by its other subchannels, and then the original controller to reconnect on the subchannel later, to complete the transfer. This made reasonable async I/O possible, without losing the benefits of the channel architecture. But 360 and 370 didn't have that, so yeah, fairly horrid terminal comms.
Show threadティージェーグレェ1d ago
Need? Probably not.

As far as wants, I still want an Amiga with an MC68060; admittedly, such things cost a lot (still) and I need (and also want) a house more than I need another computer. So that my meager material possessions aren't stuck in storage. Also, the Amiga 4000 wasn't an SBC, IIRC the CPU was on a separate PCB (which made CPU "upgrades" easier I guess!).

Can new MC68060s even be purchased in 2026? I think NXP maybe owns the rights (Motorola sold them to Freescale which in turn was acquired by NXP if I remember correctly) but I don't think they're still fabbing anything related to them? Sourcing such parts in the after market (I look for such things, on the off chance I may be able to populate the Amiga 4000 reverse engineered PCB I bought years ago) and they're few and far between.

I'm not too interested in old 32-bit RISC based systems either, or new systems, based on old 32-bit RISC designs.

Though, I did just buy a few 32-bit RISC-V based thingamajigs they were like, $10 a piece, so not exactly bank breaking.
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@teajaygrey
Motorola Semiconductor was spun off as Freescale, and purchased by NXP.
The MC68060 hasn't been made for many years. They can usually be found on eBay for $300 to $500. Caveat Emptor.
I'm not designing this to be compatible with any existing computer, or to have video output, etc., though maybe those could be added. My own use case is just to run BSD on them.
Show threadthe vessel of morganna1d ago
@brouhaha I would totally buy something like this if it could run say, NetBSD
Show threadπŸ‡ΊπŸ‡¦ haxadecimal πŸš«πŸ‘‘1d ago
@astraleureka
NetBSD is what I want to run, but I don't know how much work the port will be.
Show threadF4GRX Sébastien18h ago
@brouhaha 68060 yeah definitely. Others not so much.
Show threadLars Brinkhoff14h ago
@brouhaha All those sound delightful. Not that I would have time to play with them, but I endorse the idea.
Show threadlymenzies6h ago

@brouhaha

I think what draws me to alternate or retro platforms is the desire to run software that isn't available elsewhere. If you were to create a MC68060 board just to run Linux or BSD, it becomes a lot less interesting.

Not because of any shortcomings to BSD or Linux, but simply because once you have those systems available, the platform becomes a lot more generic.

When I think of retro systems I'd like a new version of, the list is pretty short.

NeXT, LISP machines, any of the early Xerox computers, MIPS-based SGI, and Lilith.

Show threadMichael Kohne1h ago
@brouhaha Hey, if anyone is interested, I have a TMS34020 ICE sitting on my shelf that I'd love to send to someone who wants it! I'm in the US, not far from Philly, I'm willing to pay most or all of the shipping within the US at least.
Show threadMichael Kohne1h ago
@brouhaha For those not familiar, the TMS34020 was a Graphics System Processor from TI back a ways - it's a neat chip with interesting features like bit-wise pointers, selectable big or little endian operation, and the inner loop or Breshenhem's algorithm as a single processor instruction. Thoroughly weird and wonderful.
Show threadMichael Kohne1h ago
@brouhaha And if anyone wants a PCB that used this thing, I might still have one or two that I trash picked from a previous employer - custom board with a DSP32 and a 68020 on it as well as the 34020.