Later in the presentation, the presenter gives an example where adding a prefetch instruction actually slows the program down, just because it was bottlenecked on instruction fetch, and the additional prefetch instruction made that part worse.

The next section was about instruction retirement. This is the part that I thought was most interesting, because I don't know much about it. Instructions have to appear to complete (or "retire") in program order.

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So the whole chip is prefetching instructions and speculatively executing what they say, and then when the results are computed, they enter into the retire unit where they hang around until they are allowed to "retire" observably in program order.

The interesting thing here is that the retire unit only holds 64 entries, but fetching from memory takes 200 cycles at a minimum. That means we can't (even nearly!) hide memory latency by running concurrent ALU.

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So, if you're going to hit memory, you'll want to manually schedule either a) expensive instructions, or b) other memory operations, concurrently, to maximize parallelism of the chip. So interesting!!!

The previous diagram also lists the number of unnamed registers, which is less than I expected (72 and 64); I expected there would be hundreds. Interesting!

Another really interesting part: it turns out that interacting with the cache is done in transactions.

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