So, at work my workstation is an i7-14700K (we're a 100% Intel shop for...reasons? not my monkeys, not my circus on this one)

Turns out the mismatched cache sizes on Intel's b̴i̴g̴.̴L̴I̴T̴T̴L̴E̴ er, "P and E core" design cause GCC to fail to bootstrap itself

Cool and normal

I especially like that because which CPU core that *checking what CPU features are available* is actually executed on is effectively "random" it's not possible to automatically resolve this, either

Shout out to the time Intel accused AMD of "gluing CPU's together" with Threadripper and Epyc

And then turned around and farted this out

@CursedSilicon meanwhile, arrow lake has 3 different microarchitectures across multiple stacked dies for… some reason

@cinebox Excuse you

It's stackedDie+++++