Miquel PericasMar 2
Intrigued by FelixCLC's talk at FOSDEM 2026 about RISC-V design decisions. Agree about RVC (compressed) instructions. Seems to add just complication without much use case. Is there a chance that future specs deprecate it? #riscv
Show threadMiquel PericasMar 2
For RVV, implicit state does sound a bit ugly. vtype can be thought as a prefix to all vector instructions, ie a way to extend them without replicating bits. Downside: lots of vsetvli insts. In practice, do we save or lose space? Are there any studies?
Show threaddzaimaMar 4
@miquelp Question is what you'd be losing space relative to; cause fitting the 5 vtype bits into the instructions with a 32-bit encoding would take up a rather massive amount of encoding space (3×5 reg bits, 5 vtype, 1 masking, leaves 11 bits of opcode (or 9 bits if not stealing RVC's encoding space) for fitting in all vector instrs, and you still have to leave space for non-vector instrs).
Show threaddzaimaMar 4
Of course going to a 64-bit bit encoding would immediately mean being at least as bad as separate vsetvl; 48-bit would work, but of course isn't particularly compatible with the other discussed idea of getting rid of RVC.
Show threaddzaima

@fclc I don't understand the particular badness of "implicit state" here though; the vtype bits are pretty cleanly just bits of the nearest preceding vsetvli/vsetivli instruction (vsetvl can just cause a stall, it's for context restore anyway).

Is it wanting to do work with instrs without yet having even fetched some preceding ones? Wanting to compute stuff before the cycle or two or whatever of the vtype being forwaded? The last-vtype forwarding taking too much area/power? Something else?

Mar 4 at 11:46amWeb
Show threaddzaimaMar 4
(granted, those hypotheses are a rather long list.. even then, those feel like weird things to complain about relative to "need to crack SIMD ops into 8 uops (or crazier things for reduces esp. vfredosum, or the billion different funky loads/stores))
Show threadFCLCMar 4
@dzaima Mainly it's that it get's very, very ugly when dealing with an OoO machine and having to track a dynamically changing view of the machine across time/space boundaries boundaries. Add in your typical race to sleep classes of problems, power dependant speculation/commit heuristics and it gets even uglier