Miquel Pericas

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Show threadMiquel PericasMar 2
Felix mentions alternate Vector specs in development. Was he referring to packed SIMD? What other (non academic) specs are being developed to replace RVV? I am guessing he did not mean IME and AME
Miquel PericasMar 2
Intrigued by FelixCLC's talk at FOSDEM 2026 about RISC-V design decisions. Agree about RVC (compressed) instructions. Seems to add just complication without much use case. Is there a chance that future specs deprecate it? #riscv
Show threadMiquel PericasMar 2
For RVV, implicit state does sound a bit ugly. vtype can be thought as a prefix to all vector instructions, ie a way to extend them without replicating bits. Downside: lots of vsetvli insts. In practice, do we save or lose space? Are there any studies?
Show threadMiquel PericasMar 2
Link to the talk: https://share.google/Ply5RlwfDOVmTfwE0
FOSDEM 2026 - RISC-V had 40 years of history to learn from: What it gets right, and what it gets hilariously wrong