Craig BishopFirst blink on this XCVU13P board! We’re barely scratching the surface here…
This is like using an Oak Ridge supercomputer to run Hello World.
I think I might be motivated to try adding SLR support to OpenFPGALoader. I'm so used to it now, it's weird using Vivado to load a bitstream.
Darrell HarmonYou might find this file useful to pull information from. It's generated by parsing all the Xilinx BSDLs. Xilinx doesn't otherwise document the multi-SLR instructions. Other than that, just a matter of extending the IR length, swapping the CFG_IN, JPROGRAM, etc instructions. No need to do anything with the SLRn ones. The tool parses for master SLR, sets the right one to the base command.
https://gitlab.com/harmoninstruments/jaytag/-/blob/main/libjaytag/src/ids/xilinx.rs?ref_type=heads
Script that generates it:
https://gitlab.com/harmoninstruments/jaytag/-/blob/main/libjaytag/tools/bsdl.py?ref_type=heads
@dlharmon In rough terms, is it like programming multiple FPGAs in parallel with an extra long IR? I've yet to dive in.
libjaytag looks cool! I'm a Rust guy too. I've been looking for something to build a few JTAG utilities on top of, and so far I had been considering probe-rs. It has raw JTAG access API layers, but it wasn't going to be pretty.
@craigjb It's really more like a single FPGA with a long IR and different opcodes.
I'll let you know when it's ready to try. Looked into probe-rs at first too and that was going to be a mess, the raw JTAG wasn't public so I'd need to fork. The idea with Jaytag is that it's layered, you can go as low level as you like.