Craig BishopFirst blink on this XCVU13P board! We’re barely scratching the surface here…
This is like using an Oak Ridge supercomputer to run Hello World.
I think I might be motivated to try adding SLR support to OpenFPGALoader. I'm so used to it now, it's weird using Vivado to load a bitstream.
Darrell HarmonYou might find this file useful to pull information from. It's generated by parsing all the Xilinx BSDLs. Xilinx doesn't otherwise document the multi-SLR instructions. Other than that, just a matter of extending the IR length, swapping the CFG_IN, JPROGRAM, etc instructions. No need to do anything with the SLRn ones. The tool parses for master SLR, sets the right one to the base command.
https://gitlab.com/harmoninstruments/jaytag/-/blob/main/libjaytag/src/ids/xilinx.rs?ref_type=heads
Script that generates it:
https://gitlab.com/harmoninstruments/jaytag/-/blob/main/libjaytag/tools/bsdl.py?ref_type=heads
@craigjb If you want to try building a very beta Rust thing via Cargo for a CLI FPGA loader, I can push something that's in a usable state.
Currently only supports FTDI based interfaces plus XVC.