@dramforever i don't get why people spend so much effort writing compilers, we could just train an AI to convert code from C to assembly
@dramforever We already had a way to spend copious amounts of time wating for code gen, it was called C++ templates.
@dramforever hi i teach a comp arch lab and i will steal this with attribution
@mosfet hi that's fine by me, but i just want to make sure, do you understand what the bottom "large code model" is referring to?
@dramforever compiler compiling C to ARM (which happens to be one of the ISAs we teach), managing stack frames and calling an external function
@dramforever is it arm though
@mosfet it's risc-v assembly, specifically in the *large* *code model*, i.e. -mcmodel=large, where symbol references require referencing a literal pool nearby the instruction itself. this allows a single executable to way exceed 2G in total data and code size, and allows static linking while putting stuff all over the place in 64-bit address space. see https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#large-code-model
riscv-elf-psabi-doc/riscv-elf.adoc at master · riscv-non-isa/riscv-elf-psabi-doc

A RISC-V ELF psABI Document. Contribute to riscv-non-isa/riscv-elf-psabi-doc development by creating an account on GitHub.

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@mosfet among other things, arm assembly would have more three-letter mnemonics (add, sub, ldr, str) whereas risc-v has no such tendency. also risc-v has mips-style register alias names (s0, t0, etc) (but with no prefix (mips would have $t0 etc)) whereas arm registers are *mostly* just referred to by number (x0 through x31 ...)
@dramforever i have been enlightened. thank you so much