FZ Jülich - ICAJun 6, 2025

We've just released 4 new pre-prints on arXiv, showcasing our latest work in neuromorphic computing, memristor-based architectures, oscillator networks, and cryogenic power management. 🧠⚡️❄️

1️⃣ 2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology
👉 https://arxiv.org/abs/2505.12830

2️⃣ Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms
👉 https://arxiv.org/abs/2505.11009

2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.

arXiv.org
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3️⃣ Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity
👉 https://arxiv.org/abs/2505.10248

4️⃣ Self Clocked Digital LDO for Cryogenic Power Management in 22nm FDSOI with 98 Percent Efficiency
👉 https://arxiv.org/abs/2505.10234

🔗 Check them out on arXiv. 📄

#arXiv #NeuromorphicComputing #Memristor #CryoCMOS #SoC #VLSI #OscillatorNetworks #LowPowerDesign

Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity

Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research.

arXiv.org
Jun 6, 2025 at 1:13pmWeb