@WillFlux Of course I want multiple pixel clocks! Heck, I want a dynamically reclockable PLL real bad and I'm still shocked this is not standard in all FPGAs... Toolchains, just let me tell you the maximum clock I'll generate and let me do my thing! No?

So what? I'm supposed to have external PLLs clocking my CRTC? Am I supposed to use a SERDES to increase my clock then step it down using a fractional divider which feeds an internal PLL with a 1:1 ratio? Or am I just supposed to support modes that have pixel clocks that have an integer ratio between them? Play with phases to generate a higher frequency clock using combinatorial logic, feeding a PLL? All of the techniques above?

It could have been sooooooo simple... At least with Xilinx we can use partial reconfiguration primitives to dynamically change the PLLs' parameters. Can't wait for prjCombine to be good-enough that I would not haveto use Vivado anymore and thus make my NeTV2 more fun to play with.