mblshaTurns out it’s possible to serialize data to 100MHz UART on the FPGA side, and have #saleae correctly decode it with 500MS/s sampling rate.
(screenshot is from Sharp PC-G850's Z80 system bus, with selected address encoded to UART)
Making address transmissions to be single 16-bit packets enables easy value search in #saleae Logic and saves a few nanoseconds between transmissions.
Also this Z80 variant has a weird counter on the address pins after reading the first instruction, will need to decode it more carefully later.
Peter Marheine@mblsha You're seeing the R register incrementing, since every M1 bus cycle is followed by a memory refresh cycle (for DRAMs).
@pmarheine whoa, thanks! Totally forgot about that being an option since the system uses only SRAM.