Accidental Tech Podcast562: Do You Have a Dragon?
https://atp.fm/562
OpenAI's turmoil, M3 Max thermals, keyboard wear, and the Humane Ai Pin.
Abhi Beckert šŗš¦@atpfm ABS plastic is harder than PBT plastic. Itās a chemical reaction with finger oil that causes ABS to wear out faster than PBT and the difference is more than 10x. Itās more complex than just double shot. All āgoodā PBT keyboards are double shot - only the cheapest Ali Express PBT keyboards are double shot with clear plasticā¦ I donāt know why but I wouldnāt buy those.
Mike Taffet@atpfm I think Iām with @caseyliss. I like my 14ā for portability primarily, with the added benefit that when I do push the CPU I wait a āminimalā amount of time for processing to complete. Itās a pretty good balance IMO. Desktop Laptop lifestyle is absolutely a different need IMO.
Christian Lynbech@miketaffet @atpfm @caseyliss Less of a problem these days, I guess, but if you plan to take your laptop onto a plane and actually use it, please remember to check seat size vs laptop size vs belly size, at least if the latter is significant (as it is for me). A 16ā demands more room and all three parameters matter š
Darin Kelkhoff@atpfm I always read the show notes the day theyāre posted, but wait until the weekend to listen. Today I thought that the SpaceX link under ERR_NETWORK_CHANGED must have been a mistake. Then I clicked the link and died a little on the inside.
Reid@atpfm Iāve been burned too many times by the āitās the same machine butā¦ (the gpu has less memory!)ā on the small MBP size so this time I went 16ā for my corp machine.
Man. It mostly sits on my desk, I rarely travel with it. But every time I pick it up or look at it with the screen open, it just feelsā¦ disappointing. Itās an aesthetic thing more than a real āI canāt lift thisā thing. It just looks wrong, oversized, clunky.
Man. It mostly sits on my desk, I rarely travel with it. But every time I pick it up or look at it with the screen open, it just feelsā¦ disappointing. Itās an aesthetic thing more than a real āI canāt lift thisā thing. It just looks wrong, oversized, clunky.
Frank Malinowski
Jai@atpfm listening to the bootleg this morning as I took delivery of my new 16ā Max, I was feeling pretty good with my decision to not go 14ā. Having just walked 3km with it in my bag on my backā¦ I think Iām still feeling good about my upgrade from an M1 Air. Quick I need to go transcode something big
@atpfm @siracusa @caseyliss @marcoarment
Did a quick size comparison of the MacBook Pro 16ā with the PowerBook G4 12ā. It blew me away that the 12 and 16 are nearly identical in weight. I remember thinking my 12ā was so tiny and lightweight twenty years ago.
MBP 16ā
90.34 cubic inches
4.7/4.8 lbs.
PowerBook 12ā
110.61 cubic inches
4.6 lbs.
PowerBook 17ā (for giggles)
157.08 cubic inches
6.9 lbs.
John Conway@frankly @atpfm @siracusa @caseyliss @marcoarment The PowerBook 12" was surprisingly thick. The thickest metal Apple laptop?
john š§
Kathryn Elrod@frankly The PowerBook was 25-30% less dense than the MBP, which is probably why it seemed lighter.
martynpie@frankly that 12ā G4 was my first Mac š„° very fond memories.
Der Teilweise@frankly @atpfm @siracusa @caseyliss @marcoarment
MBP 16" (40.6 cm)
1480 cmĀ³ (1.5l)
2132g/2177g (2.1 kg/2.2 kg)
PowerBook 12" (30.5 cm)
1813 cmĀ³ (1.8l)
2087g (2.1kg)
PowerBook 17" (43.2 cm)
2574 cmĀ³ (2.5l)
3130g (3.1kg)
Johan Malmstrƶm@atpfm Where is Sam today?
Joe Lion@atpfm there was a bad edit at 39:09 so maybe I missed some discussion. But Casey (as Pat Gelsinger, I think?) talked about a 3D construct of moving SRAM cache to a base die and put "advanced computing on top in a 3D sandwichā. John responded that this was a technology that Intel is advancing to to route power through the layers of the sandwich more efficiently. While Intel IS doing that, based on what Pat was saying, I'm quite sure that's not what he was talking about in that instance. 1/10?
@atpfm He was talking about the chiplet and chip-stacking architecture, which John also talked discussed soon after, where SRAM is going to be moved onto dedicated dies on older N-x nodes, then 3D stacked onto the CPU chip. The High Yield youtube channel has been making good videos about the problems with SRAM scaling:
Next-Gen CPUs/GPUs have a HUGE problem!
@atpfm A typical CPU die now looks like, from bottom-to-top: a pure silicon substrate (the bulk of the silicon that makes up the wafer); the transistors, build directly on, immediately below, and immediately above the surface of the Si; a dozen+ metal layers, providing interconnects and signal routing between transistors and circuit blocks; and finally another few metal layers that carry power across the chip.
4/10?
4/10?
@atpfm
The metal layer dimensions grow as they get higher (the most narrow signals in lower layers, then larger/wider signals near the top). The power busses have are made in the upper metal layers, because power signals need wide wires and they need to cross large areas of the chip, in order to bridge between circuit blocks and to route power from the power supplies to the functional circuits.
5/x
The metal layer dimensions grow as they get higher (the most narrow signals in lower layers, then larger/wider signals near the top). The power busses have are made in the upper metal layers, because power signals need wide wires and they need to cross large areas of the chip, in order to bridge between circuit blocks and to route power from the power supplies to the functional circuits.
5/x
@atpfm However, the power also needs to make its way down to the actual transistors, at the Si surface, so metal Vias have to snake their way down from the very upper top layers, through and around 15+ other metals layers (without interfering with them or adding noise), then finally make contact with the active areas on the Silicon directly.
6/x
6/x
@atpfm Intels Backside Power Delivery, or PowerVia, says āhey - you know all of that silicon substrate, below the transistor wells, that's not really doing anything except providing structural integrity for the chip? What if we built the power busses INTO the substrate, UNDER the transistors, but still on the same die?ā That way, power bus layers are physically separated from signal layers, reducing noise and routing complexity.
7/x
7/x
@atpfm Power can be connected to the bottom of the transistors instead of the tops, which is just as well - the transistors don't care. And by removing all of the power connections on the top of the transistors, signal routing and transistor layout and density can be optimized even more. But, this means building a whole new world of signals on the OTHER side of the wafer.
8/9
8/9
@atpfm Up to now, wafers go through a fab, and all structures, starting from the transistors and going up to the top metal, are built from the bottom up, building on top of one side of the wafer only. But, with Backside Power, they will build on one side of the wafer, then turn the wafer over, grind it down incredibly thin, then create a whole other set of layers on the backside of the wafer, tunneling through to connect to the transistors they made on the front side.
9/10
9/10
@atpfm All while not messing up all of the transistors and layers they already made on the front! Incredible stuff.
https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
10/10
Mike@atpfm for the person wondering what to do with their kids art, try Artkive! They send you a box where you can put all the art worth keeping and when itās full you send it in and they make a book or wall print. https://bf.artkivebox.com/?param_5=tiktok25
@atpfm was I the only one who at first thought this is what was meant by āpackagingā?
chanomie@atpfm I take medication that makes my sweat have a very high acidity. On my old 16ā PowerBook G4 laptop, lots of tiny holes got eaten into aluminum case where my wrists rested. But, I guess my fingertips arenāt sweaty enough as Iāve never lost the paint on my key caps. And I have much more ergonomic typing now and donāt rest my wrists.
Eric deRuiter@atpfm Worth noting that iCloud Private Relay does use QUIC. I donāt know if that means Safari or other apps are vulnerable to ERR_NETWORK_CHANGED when it is on. https://developer.apple.com/support/prepare-your-network-for-icloud-private-relay
roland lebrun
Andrew Herron@atpfm I haven't bought a shirt since "slaccidental tech podcast" and "butterfly" in 2019, between shipping to Australia and the exchange rate it just hurts too much (now AU$87 for one US$39 shirt).
But I would 1000% buy an "err network changed" related shirt š¤£
Antony Johnston@atpfm @marcoarment Your comment re screens makes me think the Humane pin is kind of equivalent to the Touch Bar š¬
Sloan Studio@atpfm Great episode. For those interested in Intel's #MeteorLake aka #CoreUltra processors, this is a pretty good video they put out that talks about their tile approach and packaging to bring it all together. https://www.youtube.com/watch?v=dpekP4lbAMw
Meteor Lake Overview: In-depth with Intel Architects and Engineers | Talking Tech | Intel Technology
Tyler@atpfm would love to hear yāall talk about the genocide happening in Palestine right now. I know you guys care about innocent people and care about using your platform to spread the word about important things. http://ceasefiretoday.com is a great website for those who feel helpless as their government funds these atrocities. Thanks guys, big fan.
Dirkjan Ochtman@atpfm the story about QUIC/H3 being at fault for ERR_NETWORK_CHANGED sounds iffy. QUIC is actually designed to cope well with network changes and the RFC describes how a QUIC connection can continue even if a network path changes (see https://www.rfc-editor.org/rfc/rfc9000.html#name-connection-migration). So if anything, QUIC connections should be more robust, not less robust, to network changes.
(I started my own QUIC implementation in Rust, https://github.com/quinn-rs/quinn, which has become decently popular.)
RFC 9000: QUIC: A UDP-Based Multiplexed and Secure Transport
This document defines the core of the QUIC transport protocol. QUIC provides applications with flow-controlled streams for structured communication, low-latency connection establishment, and network path migration. QUIC includes security measures that ensure confidentiality, integrity, and availability in a range of deployment circumstances. Accompanying documents describe the integration of TLS for key negotiation, loss detection, and an exemplary congestion control algorithm.