Jose Morales
just watching https://www.youtube.com/watch?v=qgmrZoJyHUw with @PythonLinks talking about #forth CPUs and the differences with other architectures. The ease of stack based CPU’s and and data alignment seem to be very appealing to me, can wait to test the #Hana-Core ! Shot out to Christopher Lozinski @PythonLinks for his work and the presentation. Thought I had was, if Forth is the Opcode, can’t you port the language VM’s to use that as their own bytecode?
Review of Soft Core Forth Processors -- Christopher Lozinski -- 2023-08-26

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Aug 27, 2023 at 6:34amWeb
Show threadVideo Processing WikiAug 27, 2023

The similarity between language vm opcodes and Forth words in hardware is promising, they share stack operations like push or pop, but if you actually read the Javascript, Python and Lua opcode references they diverge from Forth. Lua 5.* is particularly different.

@jemo07

Show threadJose MoralesAug 27, 2023
Yes, high-level languages are interpreted to VM bytecode, (which are all different )often optimized by JIT compilers. What I meant was, If the VM bytecode is #forth, wouldn't it essentially be optimized machine code for a #forthCPU? I'm intrigued by the potential of softCores and am exploring their best use cases. Great talk! @PythonLinks
#python
#SoftCoreCPU
#Forth
#VM
#Bytecode
#JITCompiler
#MachineCode
#HighLevelLanguages
#TechTalk
#Optimization
#Programming
Show threadVideo Processing WikiAug 27, 2023

The forth words of a Forth Core are the byte codes of a Forth vm.
Take a closer look at Ting's EP16/24/32/64. His focus was on a very portable forth, which did exactly that.
#Mecrisp does the same thing, but more by adapting existing software to the J1, than as an explicit design goal.

There is a version of EForth for the J1.

@jemo07

Show threadJose MoralesAug 27, 2023
Absolutely, I'm familiar with the concept. The #svfig talk touched on implementing high-level languages with a #softcore #forth. It's intriguing to consider for its broader success a #vm that compiles Forth bytecode, be it forth, python, or lua. FYI, I'm exploring Verilog with my own untested implementation: https://github.com/jemo07/MyFPGA_FORTH. @PythonLinks
GitHub - jemo07/MyFPGA_FORTH: FPGA FORTH CPU

FPGA FORTH CPU. Contribute to jemo07/MyFPGA_FORTH development by creating an account on GitHub.

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