Oooh! I just learned that some of the AMD (Xilinx) Spartan Ultrascale+ FPGAs have a moderately large number of "HD" (high density) I/O pins. More than 300 in the biggest parts, which don't yet appear to be out.
"HD" don't cover as many obscure I/O standards as the old "HR" (high range 1.2V to 3.3V) I/Os, but at least they do cover that voltage range.
For a while, it was looking like AMD/Xilinx were moving away from providing 3.3V capable I/O pins.
#fpga #amd #xilinx #spartan #ultrascaleplus