Gave a talk yesterday:
"Property Based Testing to verify a pipelined CPU design (hardware)"
at the New England Programming Languages and Systems Symposium (NEPLS),
about verifying my Fife RISC-V CPU using U.Cambridge's TestRIG (which uses Haskell's QuickCheck) and RISC-V International's RISC-V ISA Formal Specification (written in Sail)

https://nepls.org/
https://nepls.org/Events/36/

#NEPLS #FIFE #RISCV #RVI #Haskell #QuickCheck #TestRIG #PBT #Sail